公开(公告)号：US10921848B2

公开(公告)日：2021-02-16

申请号：US15735362

申请日：2016-06-23

Applicant: ARM Limited

Inventor： Ramnath Bommu Subbiah Swamy

IPC: G06F1/10 ,  G06F1/12 ,  G06F1/06

Abstract: An integrated circuit includes multiple blocks of circuitry (4, 6, 8) communicating signals via an interface 10 controlled by a clock signal. A clock mesh (20, 22) is used on at least one side of the interface driven by one or more clock drivers (24, 26) that drive the clock mesh with the clock signal communicated with a further block of circuitry. A plurality of interface storage circuits (flip-flops) (12, 14, 16, 18) are coupled to the clock mesh and receive the clock signal from the clock mesh to control storage therein. The interface storage circuits (54) may be of a form controlled by multiple clock signals, CP0, CP1. A signal value D may be captured into the storage circuit upon a rising edge of a first clock signal CP0 and launched from the storage circuit upon the rising edge of a second clock signal CP1.

公开(公告)号：US10530562B2

公开(公告)日：2020-01-07

申请号：US15493429

申请日：2017-04-21

Applicant: ARM Limited

Inventor： Richard Andrew Paterson ,  Simon Crossley ,  Ramnath Bommu Subbiah Swamy ,  Steven Douglas Krueger ,  Anitha Kona

IPC: G06F1/12 ,  H04L12/26 ,  H04L7/00

Abstract: A method for correlating first and second local time counts in first and second integrated circuits is provided. The first and second integrated circuits communicate via a communication network. A separate time control signal path is also provided between the integrated circuits. The method comprises determining a signal propagation latency associated with propagation of a latency determining signal between the integrated circuits on the time control signal path, and correlating the first and second local time counts in dependence on the signal propagation latency and a time correlating signal transmitted on the time control signal path.

公开(公告)号：US09715912B2

公开(公告)日：2017-07-25

申请号：US14696685

申请日：2015-04-27

Applicant: ARM LIMITED

Inventor： Ramnath Bommu Subbiah Swamy

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F13/16 ,  G11C7/1051 ,  Y02D10/14

Abstract: An integrated circuit device comprises a first data processing element having a first data interface configured to synchronously communicate data according to a first clock signal at a first clock speed, and a second data interface configured to synchronously communicate data at a second clock speed lower than the first clock speed; and a second data processing element configured to operate in response to a second clock signal at the second clock speed and to synchronously communicate data with the first data processing element via the second data interface according to the second clock speed; the first data processing element being configured to derive, from a source clock signal, the first clock signal and the second clock signal; and the first data processing element and the second data processing element each comprising a clock signal interface by which the second clock signal is provided by the first data processing element to the second data processing element.