公开(公告)号：US20140272184A1

公开(公告)日：2014-09-18

申请号：US14179019

申请日：2014-02-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Subbalakshmi SREEKALA ,  Xinhai HAN ,  Nagarajan RAJAGOPALAN ,  Bok Hoen KIM ,  Yoichi SUZUKI ,  Tsutomu KIYOHARA

IPC: C23C16/44

CPC classification number: C23C16/4404 ,  C23C16/0245 ,  C23C16/308 ,  C23C16/402 ,  C23C16/4405

Abstract: Methods for maintaining clean etch rate and reducing particulate contamination with PECVD of amorphous silicon films are provided. The method comprises cleaning a processing chamber with a plasma comprising a cleaning gas, exposing at least a portion of the interior surfaces and components of the processing chamber to an oxidation gas and a nitration gas in the presence of a plasma and depositing a bi-layer seasoning layer on the interior surfaces and components of the processing chamber.

Abstract translation: 提供了通过非晶硅膜的PECVD保持清洁蚀刻速率和减少颗粒污染的方法。 该方法包括用包括清洁气体的等离子体清洁处理室，在等离子体存在下将处理室的至少一部分内表面和组分暴露于氧化气体和硝化气体中，并沉积双层 处理室的内表面和部件上的调味层。

公开(公告)号：US20160260602A1

公开(公告)日：2016-09-08

申请号：US14400735

申请日：2014-10-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Subbalakshmi SREEKALA ,  Nagarajan RAJAGOPALAN ,  Bok Hoen KIM

IPC: H01L21/02 ,  H01L21/324

CPC classification number: H01L21/02274 ,  C23C16/24 ,  C23C16/402 ,  C23C16/4408 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02301 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/32055 ,  H01L21/324 ,  H01L27/11556 ,  H01L27/11582

Abstract: Embodiments generally relate to methods of controlling hydrogen content in a silicon oxide/amorphous silicon stack. By precleaning the substrate of residues, controlling the delivery of hydrogen during the stack deposition and preventing outgassing of hydrogen from deposited layers during subsequent layer deposition and processing, the effects of delamination can be avoided in the formation of devices, such as 3D NAND devices.

Abstract translation: 实施例通常涉及控制氧化硅/非晶硅堆叠中的氢含量的方法。 通过预清洗残余物的底物，控制在堆叠沉积期间氢的输送，并且在随后的层沉积和处理期间防止氢从沉积层中脱气，在形成诸如3D NAND器件的器件中可以避免分层的影响。

公开(公告)号：US20160203971A1

公开(公告)日：2016-07-14

申请号：US14879043

申请日：2015-10-08

Applicant: Applied Materials, Inc.

Inventor： Michael TSIANG ,  Praket P. JHA ,  Xinhai HAN ,  Nagarajan RAJAGOPALAN ,  Bok Hoen KIM ,  Tsutomu KIYOHARA ,  Subbalakshmi SREEKALA

IPC: H01L21/02 ,  H01L27/115

CPC classification number: H01L21/0217 ,  H01L21/02274 ,  H01L27/11582

Abstract: Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate.

Abstract translation: 本公开的实施例提供了在半导体衬底上制造具有最小光刻重叠误差的膜层的方法和系统。 在一个实施例中，用于在衬底上形成膜层的方法包括将包含含硅气体和反应气体的沉积气体混合物供给到设置在处理室中的衬底支撑体上的衬底上，在存在 在处理室中沉积气体混合物，将电流施加到设置在处理室中的等离子体轮廓调制器，同时将沉积气体混合物供应到处理室中，并且在衬底上沉积膜层的同时旋转衬底。