FEOL LOW-K SPACERS
    3.
    发明申请
    FEOL LOW-K SPACERS 审中-公开

    公开(公告)号:US20160005833A1

    公开(公告)日:2016-01-07

    申请号:US14323855

    申请日:2014-07-03

    Abstract: Transistors and their methods of formation are described. Low dielectric constant material (e.g. a void) is placed between an elongated gate and a contact to increase the attainable switching speed of the gate of the device. An elongated structural slab of silicon nitride is temporarily positioned on both sides of the gate. Silicon oxide is formed over the silicon nitride slabs and the gate. Contacts are formed through the silicon oxide. The silicon oxide is selectively etched back to expose the silicon nitride slab. A portion or all the silicon nitride slab is removed and replaced with low-K dielectric or any dielectric with an air-gap to enable higher switching speed of the transistor. The highly-selective silicon nitride etch uses remotely excited fluorine and a very low electron temperature in the substrate processing region.

    Abstract translation: 描述了晶体管及其形成方法。 低介电常数材料(例如空隙)放置在细长栅极和触点之间,以增加器件栅极的可达到的开关速度。 细长的氮化硅结构板临时定位在浇口的两侧。 在氮化硅板和栅极上形成氧化硅。 触点通过氧化硅形成。 选择性地回蚀氧化硅以暴露氮化硅板。 去除一部分或全部氮化硅板,并用低K电介质或具有气隙的任何电介质代替晶体管的更高的开关速度。 高选择性氮化硅蚀刻在基板处理区域中使用远程激发的氟和非常低的电子温度。

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