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公开(公告)号：US11916033B2
公开(公告)日：2024-02-27
申请号：US17588525
申请日：2022-01-31
发明人： Glenn Rinne , Daniel Richter
IPC分类号： H01L23/00 , H01L23/498
CPC分类号： H01L24/14 , H01L23/49838 , H01L24/06 , H01L24/11 , H01L24/13 , H01L23/49816 , H01L24/81 , H01L2224/06051 , H01L2224/06177 , H01L2224/119 , H01L2224/11849 , H01L2224/131 , H01L2224/13012 , H01L2224/13014 , H01L2224/13015 , H01L2224/13016 , H01L2224/13017 , H01L2224/14051 , H01L2224/14131 , H01L2224/14133 , H01L2224/14135 , H01L2224/14141 , H01L2224/14151 , H01L2224/14153 , H01L2224/14154 , H01L2224/14177 , H01L2224/81815 , H01L2924/10156 , H01L2924/15311 , H01L2224/119 , H01L21/78 , H01L2224/11849 , H01L2224/13012 , H01L2924/00012 , H01L2224/13016 , H01L2924/00012 , H01L2224/14177 , H01L2224/14131 , H01L2224/14135 , H01L2224/13014 , H01L2924/00012 , H01L2224/14154 , H01L2924/00012 , H01L2224/14177 , H01L2224/14154 , H01L2224/81815 , H01L2924/00014 , H01L2224/131 , H01L2924/014
摘要： Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.
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公开(公告)号：US20220157755A1
公开(公告)日：2022-05-19
申请号：US17588525
申请日：2022-01-31
发明人： Glenn Rinne , Daniel Richter
IPC分类号： H01L23/00 , H01L23/498
摘要： Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.
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