公开(公告)号：US12026380B2

公开(公告)日：2024-07-02

申请号：US17854903

申请日：2022-06-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Mark Fowler ,  Anthony Asaro ,  Vydhyanathan Kalyanasundharam

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0679

Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.

公开(公告)号：US20180165872A1

公开(公告)日：2018-06-14

申请号：US15374752

申请日：2016-12-09

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Laurent Lefebvre ,  Michael Mantor ,  Mark Fowler ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi ,  Christopher J. Brennan

IPC: G06T15/40 ,  G06T15/80

CPC classification number: G06T15/405 ,  G06T11/40 ,  G06T15/005 ,  G06T15/80

Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.

公开(公告)号：US20160378674A1

公开(公告)日：2016-12-29

申请号：US14747944

申请日：2015-06-23

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gongxian Jeffrey Cheng ,  Mark Fowler ,  Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Mike Mantor ,  Raja Koduri

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/1072 ,  G06F12/1081 ,  G06F15/163 ,  G06F2212/1016 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/251

Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.

Abstract translation: 处理器对处理器的异构处理单元使用相同的虚拟地址空间。 处理器对不同类型的处理单元（例如CPU和GPU）采用不同的页表，其中存储器管理单元使用每组页表来将虚拟地址空间的虚拟地址转换为存储器模块的相应物理地址 与处理器相关联。 随着数据在内存模块之间迁移，可以更新页表中的物理地址，以反映每个处理单元的数据的物理位置。

公开(公告)号：US20140292756A1

公开(公告)日：2014-10-02

申请号：US13853422

申请日：2013-03-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Michael MANTOR ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kallio Kia ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T1/20 ,  G06T15/80

CPC classification number: G06T15/005

Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.

Abstract translation: 提供了一种系统，方法和计算机程序产品，用于具有延迟原始批次分组的混合渲染。 从原始序列生成原始批次。 初始批次拦截中的原始字符串标识。 识别用于处理的仓。 该箱对应于屏幕空间的一个区域。 处理识别的仓的图元的像素。 识别旁边的截距，同时处理拦截识别的bin的原语。

公开(公告)号：US20240135626A1

公开(公告)日：2024-04-25

申请号：US18402315

申请日：2024-01-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.

公开(公告)号：US20230195626A1

公开(公告)日：2023-06-22

申请号：US17558008

申请日：2021-12-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Saurabh Sharma ,  Jeremy Lukacs ,  Hashem Hashemi ,  Gianpaolo Tommasi ,  Guennadi Riguer ,  Mark Fowler ,  Randy Ramsey

IPC: G06F12/0806 ,  G06F12/10

CPC classification number: G06F12/0806 ,  G06F12/10 ,  G06F2212/1016

Abstract: A processing system is configured to translate a first cache access pattern of a dispatch of work items to a cache access pattern that facilitates consumption of data stored at a cache of a parallel processing unit by a subsequent access before the data is evicted to a more remote level of the memory hierarchy. For consecutive cache accesses having read-after-read data locality, in some embodiments the processing system translates the first cache access pattern to a space-filling curve. In some embodiments, for consecutive accesses having read-after-write data locality, the processing system translates a first typewriter cache access pattern that proceeds in ascending order for a first access to a reverse typewriter cache access pattern that proceeds in descending order for a subsequent cache access. By translating the cache access pattern based on data locality, the processing system increases the hit rate of the cache.

公开(公告)号：US20200042348A1

公开(公告)日：2020-02-06

申请号：US16050948

申请日：2018-07-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/48 ,  G06F12/1009 ,  G06F12/14 ,  G06F9/52 ,  G06F9/54 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

公开(公告)号：US20190122417A1

公开(公告)日：2019-04-25

申请号：US16179376

申请日：2018-11-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T15/00

Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.

公开(公告)号：US20180173649A1

公开(公告)日：2018-06-21

申请号：US15385566

申请日：2016-12-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Rostyslav Kyrychynskyi ,  Anthony Asaro ,  Kostantinos Danny Christidis ,  Mark Fowler ,  Michael J. Mantor ,  Robert Scott Hartog

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/161 ,  G06F13/1673 ,  G06F13/4068

Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.

公开(公告)号：US20250004653A1

公开(公告)日：2025-01-02

申请号：US18756976

申请日：2024-06-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Mark Fowler ,  Anthony Asaro ,  Vydhyanathan Kalyanasundharam

IPC: G06F3/06

Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.