公开(公告)号：US20110107064A1

公开(公告)日：2011-05-05

申请号：US12915158

申请日：2010-10-29

Applicant: Hiroaki NAKAYA ,  Yuki Kondoh ,  Makoto Ishikawa

Inventor： Hiroaki NAKAYA ,  Yuki Kondoh ,  Makoto Ishikawa

IPC: G06F9/30

CPC classification number: G06F9/382 ,  G06F9/30149 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3802 ,  G06F9/3822

Abstract: The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.

Abstract translation: 本发明在包括具有前缀的指令的指令集上实现有效的超标量指令问题和低功耗。 采用指令取出单元，其判定指令码是否是前缀码，也可以是除了指令码以外的指令码，并输出确定结果和16位指令码。 与此同时，基于确定结果解码指令代码的解码器和分别解码前缀码的解码器分别设置。 此外，在固定长度指令代码（如16位修改）之前，将前缀提供给每个解码器。 与前缀码相邻的固定长度指令代码被提供给与前缀码的解码器相同的流水线的每个解码器。

公开(公告)号：US20080288687A1

公开(公告)日：2008-11-20

申请号：US12176714

申请日：2008-07-21

Applicant: Yuki KONDOH

Inventor： Yuki KONDOH

IPC: G06F13/40

CPC classification number: G06F12/1441 ,  G06F12/1425

Abstract: A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.

Abstract translation: 一种半导体器件，包括：第一从器件; 输出第一请求控制信号和第一访问地址信号的第一主设备; 输出第二请求控制信号和第二存取地址信号的第二主设备; 连接到第一从设备的系统总线，第一主设备和第二主设备，以及当从第一主设备输出第一请求控制信号时，选择并输出第一请求控制信号或第二请求控制信号;以及 第二请求控制信号从第二主设备输出; 以及范围设置寄存器，其保存允许所述第一主设备的访问的地址范围，其中如果所述第一访问地址信号超出所述地址范围，则所述系统总线阻塞所述第一请求控制信号。

公开(公告)号：US07356649B2

公开(公告)日：2008-04-08

申请号：US10520653

申请日：2002-09-30

Applicant: Yuki Kondoh ,  Tatsuya Kamei ,  Makoto Ishikawa

Inventor： Yuki Kondoh ,  Tatsuya Kamei ,  Makoto Ishikawa

IPC: G06F12/00

CPC classification number: G06F12/0888

Abstract: A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.

Abstract translation: 半导体数据处理器具有构成高速缓冲存储器的第一存储器（6），能够由第一存储器构成可高速缓存区域或不可缓存区域的第二存储器（20），以及能够执行 当第二存储器被读取访问作为不可缓存区域时，用于输出与读访问相对应的数据的操作。 用于第二存储器的可缓存区域和不可缓存区域的指定由第二存储器映射到的存储器空间的可缓存区域或不可缓存区域的指定来确定。 该指定可以在数据处理器的操作模式下执行，或者例如设置控制寄存器。

公开(公告)号：US08813070B2

公开(公告)日：2014-08-19

申请号：US12958687

申请日：2010-12-02

Applicant: Tohru Nojiri ,  Yuki Kondoh

Inventor： Tohru Nojiri ,  Yuki Kondoh

IPC: G06F9/455 ,  G06F13/10

CPC classification number: G06F9/45533 ,  G06F9/4411 ,  G06F9/45541 ,  G06F13/102 ,  G06F13/105

Abstract: This invention is intended to reduce the hypervisor overhead. In the data processor disclosed herein, when a device driver calls for access to a control register to activate a process of a dedicated controlled peripheral device, the access is handled directly without intervention of processing by the hypervisor. When an interrupt is generated from a dedicated controlled peripheral device, a process is directly initiated by the device driver of the operating system governing the peripheral device without intervention of processing by the hypervisor. By implementing this manner of control in the processor, it becomes possible to carry out peripheral device control without intervention of processing by the hypervisor. Thereby, the hypervisor overhead is alleviated.

Abstract translation: 本发明旨在减少管理程序开销。 在本文公开的数据处理器中，当设备驱动程序要求访问控制寄存器以激活专用受控外围设备的处理时，直接处理访问，而不用管理程序进行处理。 当从专用的受控外围设备产生中断时，由管理外围设备的操作系统的设备驱动程序直接发起一个过程，而不会由管理程序进行处理。 通过在处理器中实现这种控制方式，可以在不经管理程序处理的情况下执行外围设备控制。 从而减轻虚拟机管理程序开销。

公开(公告)号：US08713563B2

公开(公告)日：2014-04-29

申请号：US11869565

申请日：2007-10-09

Applicant: Yuki Kondoh ,  Takashi Matsumoto ,  Keisuke Toyama ,  Toru Nojiri

Inventor： Yuki Kondoh ,  Takashi Matsumoto ,  Keisuke Toyama ,  Toru Nojiri

IPC: G06F9/455

CPC classification number: G06F9/5077 ,  G06F9/45558 ,  G06F2009/45583

Abstract: A data processor includes: a central processing unit (CPU), in which a plurality of virtual machines (101), each running an application program under controls of different operating systems, and a virtual machine manager (190) for controlling the plurality of virtual machines are selectively arranged according to information set in mode registers (140, 150, 151); and a resource access management module (110) for managing access to hardware resource available for the plurality of virtual machines. The resource access management module accepts, as inputs, the information set in the mode registers and access control information of the central processing unit to the hardware resource, compares the information thus input with information set in a control register, and controls whether or not to permit access to the hardware resource in response to the access control information. As a result, redesign involved in changes in system specifications can be reduced, and a malfunction owing to resource contention can be prevented. The invention contributes to increase of security.

Abstract translation: 数据处理器包括：中央处理单元（CPU），其中在不同操作系统的控制下运行应用程序的多个虚拟机（101）和用于控制多个虚拟机的虚拟机器管理器（190） 根据在模式寄存器（140,150,151）中设置的信息来选择性地布置机器; 以及用于管理对可用于所述多个虚拟机的硬件资源的访问的资源访问管理模块（110）。 资源访问管理模块将在模式寄存器中设置的信息和中央处理单元的访问控制信息作为输入接受到硬件资源，将由此输入的信息与设置在控制寄存器中的信息进行比较，并且控制是否 响应于访问控制信息允许访问硬件资源。 因此，可以减少涉及系统规格变化的重新设计，并且可以防止由于资源争用引起的故障。 本发明有助于提高安全性。

公开(公告)号：US09798679B2

公开(公告)日：2017-10-24

申请号：US12892645

申请日：2010-09-28

Applicant: Yuki Kondoh

Inventor： Yuki Kondoh

IPC: G06F12/02 ,  G06F12/14

CPC classification number: G06F12/1441 ,  G06F12/1425

Abstract: A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.

公开(公告)号：US08924689B2

公开(公告)日：2014-12-30

申请号：US12915158

申请日：2010-10-29

Applicant: Hiroaki Nakaya ,  Yuki Kondoh ,  Makoto Ishikawa

Inventor： Hiroaki Nakaya ,  Yuki Kondoh ,  Makoto Ishikawa

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/382 ,  G06F9/30149 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3802 ,  G06F9/3822

Abstract: The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.

Abstract translation: 本发明在包括具有前缀的指令的指令集上实现有效的超标量指令问题和低功耗。 采用指令取出单元，其判定指令码是否是前缀码，也可以是除了指令码以外的指令码，并输出确定结果和16位指令码。 与此同时，基于确定结果解码指令代码的解码器和分别解码前缀码的解码器分别设置。 此外，在固定长度指令代码（如16位修改）之前，将前缀提供给每个解码器。 与前缀码相邻的固定长度指令代码被提供给与前缀码的解码器相同的流水线的每个解码器。

公开(公告)号：US08706996B2

公开(公告)日：2014-04-22

申请号：US12844800

申请日：2010-07-27

Applicant: Yuki Kondoh ,  Tohru Nojiri

Inventor： Yuki Kondoh ,  Tohru Nojiri

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F9/30101 ,  G06F9/3824 ,  G06F12/1458

Abstract: The data processor can form a system including a combination of two or more operating systems running in parallel, which achieves a higher data transfer rate between operating systems and the increase in system performance without impairing the system reliability. In the system, data transfer between domains is performed in an enhanced access mode as well as an access mode in which an access from a domain manager having control of domains is handled as one from the domain manager. The enhanced access mode is arranged by enhancing, to a CPU scale, an access mode in which an access from the domain manager is treated as an access from a software program working on a domain, and the software program of domain manager transfers data between the domains. For example, in case that the domain manager performs data transfer between domains in the enhanced access mode, a read access from the domain manager is disguised as a read access from a first domain, and a write access from the domain manager is disguised as a write access from a second domain.

Abstract translation: 数据处理器可以形成包括并行运行的两个或多个操作系统的组合的系统，其在操作系统之间实现更高的数据传输速率，并且在不损害系统可靠性的情况下提高系统性能。 在系统中，域之间的数据传输以增强的访问模式以及访问模式进行，其中来自具有域的控制的域管理员的访问被从域管理器处理为一个。 通过将来自域管理器的访问视为来自在域上工作的软件程序的访问的访问模式，增强访问模式被设置为CPU规模，并且域管理器的软件程序在 域名 例如，如果域管理器在增强访问模式下执行域之间的数据传输，则来自域管理器的读取访问被伪装成来自第一域的读取访问，并且来自域管理器的写入访问被伪装为 从第二个域写入访问。

公开(公告)号：US20110131577A1

公开(公告)日：2011-06-02

申请号：US12958687

申请日：2010-12-02

Applicant: Tohru NOJIRI ,  Yuki Kondoh

Inventor： Tohru NOJIRI ,  Yuki Kondoh

IPC: G06F9/455

CPC classification number: G06F9/45533 ,  G06F9/4411 ,  G06F9/45541 ,  G06F13/102 ,  G06F13/105

Abstract: This invention is intended to reduce the hypervisor overhead. In the data processor disclosed herein, when a device driver calls for access to a control register to activate a process of a dedicated controlled peripheral device, the access is handled directly without intervention of processing by the hypervisor. When an interrupt is generated from a dedicated controlled peripheral device, a process is directly initiated by the device driver of the operating system governing the peripheral device without intervention of processing by the hypervisor. By implementing this manner of control in the processor, it becomes possible to carry out peripheral device control without intervention of processing by the hypervisor. Thereby, the hypervisor overhead is alleviated.

Abstract translation: 本发明旨在减少管理程序开销。 在本文公开的数据处理器中，当设备驱动程序要求访问控制寄存器以激活专用受控外围设备的处理时，直接处理访问，而不用管理程序进行处理。 当从专用的受控外围设备产生中断时，由管理外围设备的操作系统的设备驱动程序直接发起一个过程，而不会由管理程序进行处理。 通过在处理器中实现这种控制方式，可以在不经管理程序处理的情况下执行外围设备控制。 从而减轻虚拟机管理程序开销。

公开(公告)号：US20110016244A1

公开(公告)日：2011-01-20

申请号：US12892645

申请日：2010-09-28

Applicant: Yuki KONDOH

Inventor： Yuki KONDOH

IPC: G06F13/40

CPC classification number: G06F12/1441 ,  G06F12/1425

Abstract: A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.

Abstract translation: 一种半导体器件，包括：第一从器件; 输出第一请求控制信号和第一访问地址信号的第一主设备; 输出第二请求控制信号和第二存取地址信号的第二主设备; 连接到第一从设备的系统总线，第一主设备和第二主设备，以及当从第一主设备输出第一请求控制信号时，选择并输出第一请求控制信号或第二请求控制信号;以及 第二请求控制信号从第二主设备输出; 以及范围设置寄存器，其保存允许所述第一主设备的访问的地址范围，其中如果所述第一访问地址信号超出所述地址范围，则所述系统总线阻塞所述第一请求控制信号。