公开(公告)号：US20080181048A1

公开(公告)日：2008-07-31

申请号：US12007855

申请日：2008-01-16

申请人： Yong-Joo Han

发明人： Yong-Joo Han

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C16/349

摘要： A memory cell accessing method may include receiving an input address, determining whether the input address has been accessed at least a predetermined number of times, and converting a memory cell enabled by the input address when it is determined that the input address has been accessed the predetermined number of times or more.

摘要翻译： 存储单元访问方法可以包括接收输入地址，确定输入地址是否已被访问至少预定次数，以及当确定输入地址被访问时转换由输入地址启用的存储单元 预定次数以上。

公开(公告)号：US20080285346A1

公开(公告)日：2008-11-20

申请号：US12219600

申请日：2008-07-24

申请人： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Chol Choe

发明人： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Chol Choe

IPC分类号： G11C16/04 ,  G11C8/00

CPC分类号： G11C8/10

摘要： A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

摘要翻译： 解码器，存储器系统及其物理位置转换方法可以检测输入地址的地址计数是否等于或大于预定值。 如果地址计数等于或大于预定值，则可以转换对应于输入地址的半导体存储器件的物理位置。

公开(公告)号：US6023436A

公开(公告)日：2000-02-08

申请号：US193273

申请日：1998-11-17

申请人： Yong-joo Han

发明人： Yong-joo Han

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/02 ,  G11C8/00

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/22

摘要： Integrated circuit memory devices having synchronized bit line selection and I/O line precharge capability include an array of memory cells, a pair of differential bit lines electrically coupled to the array of memory cells, a pair of differential input/output lines and a sense amplifier electrically coupled to the pair of differential input/output lines. An equalization circuit is also provided to equalize the potentials of the pair of differential input/output lines in response to a precharge enable signal. A column select circuit is provided to electrically connect the pair of differential bit lines to the pair of differential input/output lines, in response to a column select enable signal. In addition, a control signal generator is provided to generate the column select enable signal and the precharge enable signal during nonoverlapping time intervals and in-sync with an external clock signal. Using these circuits, the timing margins (e.g., overplus operation margin) associated with the enabling of the precharge signal upon the disabling of the column select signal can be advantageously reduced to enable higher speed operation.

摘要翻译： 具有同步位线选择和I / O线预充电功能的集成电路存储器件包括存储器单元阵列，电耦合到存储器单元阵列的一对差分位线，一对差分输入/输出线和读出放大器 电耦合到该对差分输入/输出线。 还提供均衡电路以响应于预充电使能信号来均衡该对差分输入/输出线的电位。 提供列选择电路以响应于列选择使能信号将该对差分位线电连接到该对差分输入/输出线。 此外，提供控制信号发生器以在非重叠时间间隔期间产生列选择使能信号和预充电使能信号，并与外部时钟信号同步。 使用这些电路，可以有利地减少与禁用列选择信号时的预充电信号的使能相关联的定时裕度（例如，超负荷操作余量），以实现更高速度的操作。

公开(公告)号：US5982688A

公开(公告)日：1999-11-09

申请号：US996918

申请日：1997-12-23

申请人： Yong-joo Han

发明人： Yong-joo Han

IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C11/407 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094

摘要： A first precharge circuit precharges a bit line to an equalization voltage during precharging operations and is disabled during charge sharing operations floating the bit line. A second precharge circuit precharges a bit line bar to an equalization voltage during precharging and charge sharing operations. Since the bit line is floated during charge sharing operations, and the bit line bar is continually precharged to an equalization voltage level, variation of the bit line bar voltage level due to a charge coupling between the bit line and the bit line bar during charge sharing is prevented. The difference in a level between the bit line and the bit line bar after the charge sharing can be detected by a sense and amplification circuit.

摘要翻译： 第一预充电电路在预充电操作期间将位线预充电到均衡电压，并且在电荷共享操作浮置位线时被禁用。 第二预充电电路在预充电和电荷共享操作期间将位线条预充电到均衡电压。 由于在电荷共享操作期间位线浮置，并且位线条被连续预充电到均衡电压电平，所以在电荷共享期间由位线和位线条之间的电荷耦合引起的位线条电压电平的变化 被阻止 电荷共享后位线和位线条之间的电平差可以由感测和放大电路检测。

公开(公告)号：US07830742B2

公开(公告)日：2010-11-09

申请号：US12007855

申请日：2008-01-16

申请人： Yong-Joo Han

发明人： Yong-Joo Han

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C16/349

摘要： A memory cell accessing method may include receiving an input address, determining whether the input address has been accessed at least a predetermined number of times, and converting a memory cell enabled by the input address when it is determined that the input address has been accessed the predetermined number of times or more.

摘要翻译： 存储单元访问方法可以包括接收输入地址，确定输入地址是否已被访问至少预定次数，以及当确定输入地址被访问时转换由输入地址启用的存储单元 预定次数以上。

公开(公告)号：US5535152A

公开(公告)日：1996-07-09

申请号：US291943

申请日：1994-08-17

申请人： Yong-Joo Han ,  Myung-Ho Bae

发明人： Yong-Joo Han ,  Myung-Ho Bae

IPC分类号： H01L27/04 ,  H01L27/02 ,  H01L27/10

CPC分类号： H01L27/0218

摘要： A power supply arrangement for a semiconductor chip includes, in a first preferred embodiment, a power supply voltage line, a ground voltage line, an intermediate voltage line, a plurality of first noise reduction capacitors connected between the intermediate voltage line and the power supply voltage line, and a plurality of second noise reduction capacitors connected between the intermediate voltage line and the ground voltage line. In a second preferred embodiment, the power supply arrangement includes a power supply voltage line, a ground voltage line, a quiet power supply voltage line, a quiet ground voltage line, a plurality of first noise reduction capacitors connected between the power supply voltage line and the quiet ground voltage line, and a plurality of second noise reduction capacitors connected between the ground voltage line and the quiet power supply voltage line.

摘要翻译： 在第一优选实施例中，用于半导体芯片的电源装置包括电源电压线，接地电压线，中间电压线，连接在中间电压线和电源电压之间的多个第一降噪电容器 并且连接在中间电压线和地电压线之间的多个第二降噪电容器。 在第二优选实施例中，电源装置包括电源电压线，接地电压线，静态电源电压线，静态接地电压线，连接在电源电压线和电源电压线之间的多个第一降噪电容器 连接在地电压线和安静电源电压线之间的多个第二降噪电容器。

公开(公告)号：US07929372B2

公开(公告)日：2011-04-19

申请号：US12219600

申请日：2008-07-24

申请人： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Choi Choe

发明人： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Choi Choe

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

摘要翻译： 解码器，存储器系统及其物理位置转换方法可以检测输入地址的地址计数是否等于或大于预定值。 如果地址计数等于或大于预定值，则可以转换对应于输入地址的半导体存储器件的物理位置。