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172 条记录 (耗时 0.044 秒)

    Internal control signal regulation circuit
    1.
    发明授权
    Internal control signal regulation circuit 有权
    内部控制信号调节电路

    公开(公告)号：US09201415B2

    公开(公告)日：2015-12-01

    申请号：US13341682

    申请日：2011-12-30

    申请人： Yong Ju Kim ,  Dae Han Kwon ,  Hae Rang Choi ,  Jae Min Jang

    发明人： Yong Ju Kim ,  Dae Han Kwon ,  Hae Rang Choi ,  Jae Min Jang

    IPC分类号： H03K19/00 ,  G05B19/042

    CPC分类号： G05B19/042 ,  G05B2219/23314 ,  G05B2219/24036 ,  G05B2219/24037

    摘要： An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.

    摘要翻译： 内部控制信号调节电路包括：编程测试单元，被配置为响应于外部控制信号检测内部控制信号，并产生选择信号，测试代码和编程使能信号; 以及代码处理单元，被配置为响应于所述选择信号接收所述测试代码或编程代码并调节所述内部控制信号。

    Filtering circuit, phase identity determination circuit and delay locked loop
    2.
    发明授权
    Filtering circuit, phase identity determination circuit and delay locked loop 有权
    滤波电路，相位识别确定电路和延迟锁定环

    公开(公告)号：US08664987B2

    公开(公告)日：2014-03-04

    申请号：US13607234

    申请日：2012-09-07

    申请人： Dae-Han Kwon ,  Yong-Ju Kim ,  Taek-Sang Song

    发明人： Dae-Han Kwon ,  Yong-Ju Kim ,  Taek-Sang Song

    IPC分类号： H03K5/00

    CPC分类号： H03L7/093 ,  H03L7/0812 ,  H03L7/235

    摘要： A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

    摘要翻译： 滤波电路包括时钟选择单元，其被配置为响应于频率信号将具有低于第一时钟的频率的第一时钟或第二时钟作为工作时钟传送;以及滤波器，被配置为对输入信号进行滤波并生成滤波的 信号与操作时钟同步。

    MAJORITY DECISION CIRCUIT
    4.
    发明申请
    MAJORITY DECISION CIRCUIT 有权
    重大决策电路

    公开(公告)号：US20130113518A1

    公开(公告)日：2013-05-09

    申请号：US13334355

    申请日：2011-12-22

    申请人： Hae-Rang Choi ,  Yong-Ju Kim ,  Oh-Kyong Kwon ,  Kang-Sub Kwak ,  Jun-Yong Song ,  Hyeon-Cheon Seol

    发明人： Hae-Rang Choi ,  Yong-Ju Kim ,  Oh-Kyong Kwon ,  Kang-Sub Kwak ,  Jun-Yong Song ,  Hyeon-Cheon Seol

    IPC分类号： H03K19/23

    CPC分类号： H03K19/0813 ,  H03K19/23

    摘要： A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.

    摘要翻译： 多数决定电路包括：多数决定单元，被配置为将第一数据与第二数据进行比较，以确定第一数据和第二数据之一是否具有更多具有第一逻辑值的位; 以及偏移应用单元，被配置为控制多数决定单元，使得多数决定单元在第一数据中具有第一逻辑值的比特数等于具有第一逻辑值的比特数在 第二数据，如果偏移量是第一相位中的第一设定值，则第一数据具有具有第一逻辑值的更多位，并且如果偏移量是第二设定值，则判定第二数据具有第一逻辑值的更多位 第二阶段

    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME
    6.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME 有权
    半导体集成电路及其驱动方法

    公开(公告)号：US20130099838A1

    公开(公告)日：2013-04-25

    申请号：US13334241

    申请日：2011-12-22

    申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    IPC分类号： H03L7/095

    CPC分类号： H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

    摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

    摘要翻译： 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

    Phase locked loop
    7.
    发明授权
    Phase locked loop 有权
    锁相环

    公开(公告)号：US08410836B2

    公开(公告)日：2013-04-02

    申请号：US12916901

    申请日：2010-11-01

    申请人： Hae-Rang Choi ,  Yong-Ju Kim ,  Jae-Min Jang

    发明人： Hae-Rang Choi ,  Yong-Ju Kim ,  Jae-Min Jang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/14 ,  H03L7/113

    摘要： A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.

    摘要翻译： 锁相环包括相位检测器，被配置为将输入时钟的相位与反馈时钟的相位进行比较以产生相位比较结果，初始频率值提供器被配置为检测输入时钟的频率并提供频率检测 结果，配置为基于相位比较结果和频率检测结果产生频率控制信号的控制器，以及响应于频率控制信号产生输出时钟的振荡器。

    ON-DIE TERMINATION CIRCUIT
    8.
    发明申请
    ON-DIE TERMINATION CIRCUIT 有权
    端子终止电路

    公开(公告)号：US20130043901A1

    公开(公告)日：2013-02-21

    申请号：US13657123

    申请日：2012-10-22

    申请人： Yong Ju KIM ,  Hyung Soo KIM ,  Hae Rang CHOI ,  Jae Min JANG

    发明人： Yong Ju KIM ,  Hyung Soo KIM ,  Hae Rang CHOI ,  Jae Min JANG

    IPC分类号： H03K17/16

    CPC分类号： H04L25/0298

    摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.

    摘要翻译： 片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

    DELAY LOCKED LOOP
    9.
    发明申请
    DELAY LOCKED LOOP 有权
    延迟锁定环

    公开(公告)号：US20120268180A1

    公开(公告)日：2012-10-25

    申请号：US13190841

    申请日：2011-07-26

    申请人： Jae-Min JANG ,  Yong-Ju Kim ,  Hae-Rang Choi

    发明人： Jae-Min JANG ,  Yong-Ju Kim ,  Hae-Rang Choi

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0816 ,  H03L7/095 ,  H03L2207/14

    摘要： A delay locked loop includes a delay unit delaying an input clock to generate an output clock, a replica delay unit delaying the output clock to generate a feedback clock, a phase comparing unit outputting a phase signal having a first or second value according to whether the phase of the feedback clock leads the phase of the input clock, a filtering unit generates a filtering signal in response to the phase signal and updates the filtering signal when a difference of count numbers of the phase signal having the first value and the second value is substantially equal to a filtering depth, a locking unit generates a locking signal in response to the filtering signal, and a control unit adjusts a delay value in response to the filtering signal and maintains the delay value when the locking signal is activated.

    摘要翻译： 延迟锁定环包括延迟单元延迟输入时钟以产生输出时钟，复制延迟单元延迟输出时钟以产生反馈时钟;相位比较单元，根据是否输出第一或第二值输出具有第一或第二值的相位信号 反馈时钟的相位导致输入时钟的相位，滤波单元响应于相位信号产生滤波信号，并且当具有第一值和第二值的相位信号的计数数的差为 基本上等于滤波深度，锁定单元响应于滤波信号产生锁定信号，并且控制单元响应于滤波信号调整延迟值，并且当锁定信号被激活时维持延迟值。