公开(公告)号：US20130070881A1

公开(公告)日：2013-03-21

申请号：US13609749

申请日：2012-09-11

申请人： Cheng-Chieh Lin ,  Jian-Yu Ding ,  Yao-Chi Wang

发明人： Cheng-Chieh Lin ,  Jian-Yu Ding ,  Yao-Chi Wang

IPC分类号： H04L7/04

CPC分类号： H03L7/1976 ,  H03L7/099 ,  H03L7/104 ,  H03L2207/06

摘要： A phase locked loop and an associated alignment method are provided. A disclosed phase locked loop receives a reference signal to provide a feedback signal. The phase locked loop is first opened. When the phase locked loop is open, a frequency range of an oscillating signal from a voltage-controlled oscillator is substantially selected. The feedback signal is provided according to the oscillation signal. After the frequency range is selected, the phase locked loop is kept open and the phases of the reference signal and the feedback signal are substantially aligned. The phase locked loop is then closed after the reference signal and the feedback signal are aligned.

摘要翻译： 提供了锁相环和相关对准方法。 所公开的锁相环接收参考信号以提供反馈信号。 首先打开锁相环。 当锁相环断开时，基本上选择来自压控振荡器的振荡信号的频率范围。 根据振荡信号提供反馈信号。 选择频率范围后，锁相环保持断开，参考信号和反馈信号的相位基本对齐。 然后在参考信号和反馈信号对齐后，闭锁环路。

公开(公告)号：US20110122965A1

公开(公告)日：2011-05-26

申请号：US12911071

申请日：2010-10-25

申请人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

发明人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

IPC分类号： H04L27/00

CPC分类号： H03C3/0966

摘要： An offset phase-locked loop (PLL) transmitter comprises a clock generator that generates a first clock signal; a detector that detects a phase difference between an input data signal and a feedback data signal to generate a control signal; a controlled oscillator, coupled to the detector, that generates an output data signal according to the control signal; a mixer, coupled to the controlled oscillator and the clock generator, that mixes the output data signal according to the first clock signal to generate the feedback data signal; and a control circuit, coupled to the detector and the controlled oscillator, that adjusts the operating frequency curve of the controlled oscillator by one of a first step distance and a second step distance smaller than the first step distance such that the control signal is substantially equal to a predetermined value.

摘要翻译： 偏移锁相环（PLL）发射机包括产生第一时钟信号的时钟发生器; 检测器，其检测输入数据信号和反馈数据信号之间的相位差，以产生控制信号; 耦合到所述检测器的受控振荡器，其根据所述控制信号产生输出数据信号; 耦合到受控振荡器和时钟发生器的混频器，其根据第一时钟信号混合输出数据信号以产生反馈数据信号; 以及耦合到所述检测器和所述受控振荡器的控制电路，其通过第一步距离和小于所述第一步距离的第二步距离之一调节所述受控振荡器的工作频率曲线，使得所述控制信号基本相等 达到预定值。

公开(公告)号：US20110080199A1

公开(公告)日：2011-04-07

申请号：US12862346

申请日：2010-08-24

申请人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

发明人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

IPC分类号： H03L7/08

CPC分类号： H03L7/1075 ,  H03L7/093 ,  H03L7/1072

摘要： A loop bandwidth control apparatus applied to a phase locked loop (PLL) includes a first loop filter module, a second loop filter module, a control module, a first switching module, and a second switching module. The first filter module and the second loop filter module output a first voltage and a second voltage, respectively. The second loop filter module has a bandwidth different from that of the first loop filter module. According to one of the first voltage and the second voltage, the control module generates a bandwidth control signal. According to the bandwidth control signal, the first switching module forms a path between a charge pump and one of the first loop filter module and the second loop filter module, and the second switching module forms a path between a voltage-controlled oscillator (VCO) and one of the first loop filter module and the second loop filter module.

摘要翻译： 应用于锁相环（PLL）的环路带宽控制装置包括第一环路滤波器模块，第二环路滤波器模块，控制模块，第一交换模块和第二交换模块。 第一滤波器模块和第二环路滤波器模块分别输出第一电压和第二电压。 第二环路滤波器模块具有与第一环路滤波器模块不同的带宽。 根据第一电压和第二电压之一，控制模块产生带宽控制信号。 根据带宽控制信号，第一开关模块形成电荷泵与第一环路滤波器模块和第二环路滤波器模块之一的路径，第二开关模块在压控振荡器（VCO） 以及第一环路滤波器模块和第二环路滤波器模块之一。

公开(公告)号：US20090213980A1

公开(公告)日：2009-08-27

申请号：US12363792

申请日：2009-02-02

申请人： Jian-Yu Ding ,  Shen-Ching Sun ,  Yao-Chi Wang ,  Chao-Tung Yang ,  Fucheng Wang ,  Shuo-Yuan Hsiao

发明人： Jian-Yu Ding ,  Shen-Ching Sun ,  Yao-Chi Wang ,  Chao-Tung Yang ,  Fucheng Wang ,  Shuo-Yuan Hsiao

IPC分类号： H03K21/00

CPC分类号： H03K23/584 ,  H03K23/665 ,  H03K23/667 ,  H03L7/193 ,  H03L7/1976

摘要： A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal. The predetermined divider cell corresponds to the determination result.

摘要翻译： 公开了一种使用多模式分频器进行分频的多模式分频器和方法。 多模式分配器包括多模式分频电路，脉冲发生电路和模数信号发生电路。 多模式分频电路包括几个串联的分频器单元，其中预定的分频器可以被旁路。 多模式分频电路根据输入频率和除数产生输出频率。 除数的范围包括多个数字间隔。 脉冲发生电路产生脉冲信号。 模数信号发生电路通过确定除数属于哪个数值间隔来产生确定结果，并且根据确定结果将预定分频器单元中的脉冲信号输入为当输出时预定分频单元参考的参考之一 模数信号。 预定的分频器单元对应于确定结果。

公开(公告)号：US07395035B2

公开(公告)日：2008-07-01

申请号：US11407954

申请日：2006-04-21

申请人： Yao-Chi Wang ,  Ying-Tang Chang

发明人： Yao-Chi Wang ,  Ying-Tang Chang

IPC分类号： H01Q11/12

CPC分类号： H04L25/0272 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D2200/0047 ,  H03D2200/009

摘要： An up-conversion mixing system with high carrier suppression, which includes first and second LPFs to filter a first and a second input signals to thereby produce a first and a second filtered signals respectively; a first amplifier to amplify the first input signal and the first filtered signal to thereby produce a first amplified signal; a second amplifier to amplify the second input signal and the second filtered signal to thereby produce a second amplified signal, wherein the second amplifier is cross-coupled with the first amplifier in order to couple the first and the second amplified signals, thereby reducing a DC offset of a differential voltage output by the first and the second differential output terminals; and a switch to receive a differential local oscillation signal to shift the first and the second amplified signals up to frequencies associated with the local oscillation signal.

摘要翻译： 一种具有高载波抑制的上变频混频系统，其包括第一和第二LPF以滤除第一和第二输入信号，从而分别产生第一和第二滤波信号; 第一放大器，用于放大第一输入信号和第一滤波信号，从而产生第一放大信号; 第二放大器，用于放大第二输入信号和第二滤波信号从而产生第二放大信号，其中第二放大器与第一放大器交叉耦合，以耦合第一和第二放大信号，从而减少DC 由第一差分输出端子和第二差分输出端子输出的差分电压的偏移; 以及接收差分本地振荡信号以将第一和第二放大信号移动到与本地振荡信号相关联的频率的开关。

公开(公告)号：US07362141B2

公开(公告)日：2008-04-22

申请号：US11407941

申请日：2006-04-21

申请人： Yao-Chi Wang ,  Ying-Tang Chang ,  Ching-Wen Pan ,  Chin-Pin Yu

发明人： Yao-Chi Wang ,  Ying-Tang Chang ,  Ching-Wen Pan ,  Chin-Pin Yu

IPC分类号： H03F3/45

CPC分类号： H03K19/00361

摘要： A logic device with low electromagnetic interference. The logic device includes a digital logic gate, a voltage-limited circuit and a current-limited circuit. The digital logic gate provides a corresponding digital logic function. The voltage-limited circuit is connected to the digital logic gate in order to provide a fixed voltage to the digital logic gate to thus reduce an output voltage swing of the digital logic gate. The current-limited circuit is connected to the digital logic gate in order to provide a fixed current to the digital logic gate to thus reduce a transient current of the digital logic gate. Accordingly, an electromagnetic interface (EMI) caused by switching of the digital logic gate is reduced with the reduced output voltage swing and transient current.

摘要翻译： 具有低电磁干扰的逻辑器件。 逻辑器件包括数字逻辑门，电压限制电路和限流电路。 数字逻辑门提供相应的数字逻辑功能。 电压限制电路连接到数字逻辑门，以便向数字逻辑门提供固定电压，从而降低数字逻辑门的输出电压摆幅。 电流限制电路连接到数字逻辑门，以便向数字逻辑门提供固定电流，从而减少数字逻辑门的瞬态电流。 因此，由于数字逻辑门的切换引起的电磁接口（EMI）随着输出电压摆幅和瞬态电流的降低而降低。

公开(公告)号：US07298203B2

公开(公告)日：2007-11-20

申请号：US11365514

申请日：2006-03-02

申请人： Yao-Chi Wang ,  Ying-Tang Chang

发明人： Yao-Chi Wang ,  Ying-Tang Chang

IPC分类号： H03F1/02

CPC分类号： H03F3/45968 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45744 ,  H03F2200/294 ,  H03F2200/372

摘要： An amplification system capable of reducing DC offset in a baseband signal, which has first and second differential output terminals, first and second low pass filters, and first and second amplifiers. The first low pass filter filters a first input signal to thus generate a first filtered signal. The first amplifier amplifies the first input signal and the first filtered signal to thus generate a first amplified signal. The second low pass filter filters a second input signal to thus generate a second filtered signal. The second amplifier amplifies the second input signal and the second filtered signal to thus generate a second amplified signal. The system couples the first and second amplified signals at the first and the second differential output terminals to thus reduce the DC offset of a differential voltage signal output by the first and second differential output terminals.

摘要翻译： 一种能够降低基带信号中具有第一和第二差分输出端，第一和第二低通滤波器以及第一和第二放大器的DC偏移的放大系统。 第一低通滤波器对第一输入信号进行滤波，从而产生第一滤波信号。 第一放大器放大第一输入信号和第一滤波信号，从而产生第一放大信号。 第二低通滤波器对第二输入信号进行滤波，从而产生第二滤波信号。 第二放大器放大第二输入信号和第二滤波信号，从而产生第二放大信号。 该系统在第一和第二差分输出端耦合第一和第二放大信号，从而减小由第一和第二差分输出端输出的差分电压信号的直流偏移。

公开(公告)号：US20050052309A1

公开(公告)日：2005-03-10

申请号：US10707867

申请日：2004-01-20

申请人： YAO-CHI WANG

发明人： YAO-CHI WANG

IPC分类号： H03K5/003 ,  H03K5/08 ,  H03M1/12 ,  H04L25/06 ,  H04L27/32

CPC分类号： H03K5/003 ,  H03K5/084 ,  H04L25/062

摘要： An automatic threshold voltage control circuit is provided. The circuit comprises a first capacitor, a clock generator, and a switching capacitor network. Wherein the switching capacitor network, receives an analog signal and a plurality of clock signals from the clock generator, where the switching capacitor network stores a portion of charges of the analog signal according to one clock signal, and outputting the portion of charges in according to another clock signal. The portion of charges being associated with the first capacitor generates a threshold voltage. A plurality of sensor control switches is adopted in the present invention in replace of the resistor in the conventional RC filter. Hence, it can be easily integrated into one chip and number of the external devices is reduced, so that hardware costs down. In addition, RC constant can be adjusted by tuning the frequency of the clock signal.

摘要翻译： 提供自动阈值电压控制电路。 电路包括第一电容器，时钟发生器和开关电容器网络。 其中开关电容网络接收来自时钟发生器的模拟信号和多个时钟信号，其中开关电容器网络根据一个时钟信号存储模拟信号的一部分电荷，并根据 另一个时钟信号。 与第一电容器相关联的电荷部分产生阈值电压。 在本发明中采用多个传感器控制开关代替传统RC滤波器中的电阻器。 因此，它可以轻松集成到一个芯片中，并减少了外部设备的数量，从而降低硬件成本。 另外，通过调整时钟信号的频率可以调整RC常数。

公开(公告)号：US09479184B2

公开(公告)日：2016-10-25

申请号：US12858315

申请日：2010-08-17

申请人： Ming-Yu Hsieh ,  Shih-Chieh Yen ,  Yao-Chi Wang

发明人： Ming-Yu Hsieh ,  Shih-Chieh Yen ,  Yao-Chi Wang

IPC分类号： H03L7/087 ,  H03L7/099

CPC分类号： H03L7/099 ,  H03L7/087 ,  H03L2207/06

摘要： A frequency calibration apparatus, applied to a phase locked loop (PLL), includes a frequency detecting module and a search module. The frequency detecting module includes a first counter, a second counter and a comparing unit. During a monitoring period, the first counter and the second counter respectively generates a first count and a second count. The comparing unit compares the first count with the second count to generate a comparison result indicating at least three situations. The search module selects a frequency curve in response to the comparison result, and calibrates configuration of a voltage controlled oscillator (VCO) according to the frequency curve.

摘要翻译： 应用于锁相环（PLL）的频率校准装置包括频率检测模块和搜索模块。 频率检测模块包括第一计数器，第二计数器和比较单元。 在监视期间，第一计数器和第二计数器分别产生第一计数和第二计数。 比较单元将第一计数与第二计数进行比较，以生成指示至少三种情况的比较结果。 搜索模块根据比较结果选择频率曲线，并根据频率曲线校准压控振荡器（VCO）的配置。

公开(公告)号：US08258878B2

公开(公告)日：2012-09-04

申请号：US12893662

申请日：2010-09-29

申请人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Hsu-Hung Chang

发明人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Hsu-Hung Chang

IPC分类号： H03L7/00

CPC分类号： H03L7/183 ,  H03C3/0916 ,  H03C3/0975 ,  H03C3/0983 ,  H03C3/0991 ,  H03L7/0898

摘要： A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.

摘要翻译： 锁相环（PLL）包括时钟产生电路，第一相位检测电路，第一环路滤波器，第一VCO，第一混频器和控制电路。 时钟发生电路产生第一时钟信号。 第一相位检测电路检测输入数据信号和反馈信号之间的相位差，并根据相位差生成检测输出信号。 耦合到第一相位检测电路的第一环路滤波器根据检测输出信号产生第一VCO控制信号。 耦合到第一VCO和时钟发生电路的第一混频器混合输出数据信号和第一时钟信号以产生反馈数据信号。 耦合到时钟发生电路和第一环路滤波器的控制电路，用于根据第一VCO控制信号调整第一时钟信号，以计算第一VCO的增益。