公开(公告)号：US20240128960A1

公开(公告)日：2024-04-18

申请号：US18127004

申请日：2023-03-28

申请人： EVE ENERGY CO., LTD.

发明人： JUN HU

IPC分类号： H03K5/08 ,  H03F3/45 ,  H03K5/02

CPC分类号： H03K5/084 ,  H03F3/45475 ,  H03K5/023

摘要： A segment selectable signal conditioning circuit and a measurement device are provided. The circuit outputs respective voltage threshold signals through various voltage threshold sub-circuits. The voltage threshold signals are preset to have different threshold values. Each segment voltage conditioning sub-circuit conditions the input voltage signal according to the corresponding conduction signal to obtain a corresponding output voltage signal. The selection circuit receives the input voltage signal and each voltage threshold signal, and compares the voltage value of the input voltage signal to the threshold value of each voltage threshold signal respectively, and outputs the corresponding conduction signal based on the comparison result to achieve segment selectable voltage signal conditioning.

公开(公告)号：US20170077914A1

公开(公告)日：2017-03-16

申请号：US14852054

申请日：2015-09-11

申请人： Knowles Electronics, LLC

发明人： Dean A. Badillo ,  Michael Jennings ,  Craig Stein

IPC分类号： H03K5/08

CPC分类号： H03K5/084

摘要： A MOSFET active-disable switch is configured to clip an incoming signal in opposing directions when in an off state. By one approach the clipping is symmetrical and accordingly the switch clips both positive and negative peaks of the incoming signal. In many application settings it is useful for the clipping to serve to decrease a predetermined kind of resultant distortion such as even order distortion. In the on state this MOSFET active-disable switch is configured to not clip the incoming signal in opposing directions.

摘要翻译： MOSFET主动禁用开关被配置为在处于关闭状态时将输入信号相对于相反方向夹持。 通过一种方法，限幅是对称的，因此开关剪切进入信号的正峰值和负峰值。 在许多应用设置中，剪辑用于减少预定类型的结果失真（例如偶数阶失真）是有用的。 在导通状态下，该MOSFET主动禁用开关被配置为不将输入信号夹在相反的方向。

公开(公告)号：US09356577B2

公开(公告)日：2016-05-31

申请号：US14457508

申请日：2014-08-12

申请人： Hector Sanchez ,  Gayathri A. Bhagavatheeswaran

发明人： Hector Sanchez ,  Gayathri A. Bhagavatheeswaran

IPC分类号： H03L5/00 ,  H03H11/24 ,  G11C11/4093 ,  H03K5/08

CPC分类号： H03H11/24 ,  G11C7/1084 ,  G11C11/4093 ,  H03H7/24 ,  H03K5/084

摘要： Receivers for memory interfaces and related methods are disclosed having pulsed control of input signal attenuation networks. Embodiments include a DC common mode attenuation network, an AC coupling network, a pulse generator, and an amplifier. The pulse generator receives the output of the amplifier and generates a pulse signal that in part controls the operation of the attenuation network. The attenuation network generates an attenuated signal having reduced DC common mode levels. This attenuated signal is combined with an AC component passed by the AC coupling network. The resulting combined signal is detected and amplified by the amplifier. Different voltage domains are used for the attenuation network and the AC coupling network as compared to the amplifier and the pulse generator. By attenuating DC common mode levels while maintaining AC signal levels, the disclosed embodiments allow for proper signal detection over a wide range of DC common mode levels.

摘要翻译： 公开了用于存储器接口和相关方法的接收机，其具有输入信号衰减网络的脉冲控制。 实施例包括DC共模衰减网络，AC耦合网络，脉冲发生器和放大器。 脉冲发生器接收放大器的输出并产生部分地控制衰减网络的操作的脉冲信号。 衰减网络产生具有降低的DC共模电平的衰减信号。 该衰减信号与由AC耦合网络传递的AC分量组合。 所得到的组合信号由放大器检测和放大。 与放大器和脉冲发生器相比，不同的电压域用于衰减网络和AC耦合网络。 通过在维持AC信号电平的同时衰减DC共模电平，所公开的实施例允许在宽范围的DC共模电平上进行适当的信号检测。

公开(公告)号：US08723583B2

公开(公告)日：2014-05-13

申请号：US13786561

申请日：2013-03-06

申请人： Novatek Microelectronics Corp.

发明人： Tse-Hung Wu

IPC分类号： H03L5/00

CPC分类号： H03K5/084 ,  H04L25/0272 ,  H04L25/0292

摘要： An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a switch circuit and a switch control circuit. The receiver has a first channel and a second channel. The first channel receives a first channel voltage, and the second channel receives a second channel voltage. According to the first channel voltage and the second channel voltage, the switch control circuit controls the switch circuit to discharge a common mode capacitor before the first terminal resistor or the second terminal resistor couple to the common mode capacitor.

摘要翻译： 接口电路包括接收器，第一端子电阻器，第二端子电阻器，开关电路和开关控制电路。 接收器具有第一通道和第二通道。 第一通道接收第一通道电压，第二通道接收第二通道电压。 根据第一通道电压和第二通道电压，开关控制电路控制开关电路在第一端子电阻器或第二端子电阻器耦合到共模电容器之前对共模电容器放电。

公开(公告)号：US20070285291A1

公开(公告)日：2007-12-13

申请号：US11717169

申请日：2007-03-13

申请人： Yasuaki Makino ,  Susumu Kuroyanagi ,  Shinji Nakatani ,  Reiji Iwamoto ,  Hideki Hosokawa ,  Norikazu Ohta

发明人： Yasuaki Makino ,  Susumu Kuroyanagi ,  Shinji Nakatani ,  Reiji Iwamoto ,  Hideki Hosokawa ,  Norikazu Ohta

IPC分类号： H03M1/12

CPC分类号： H03K5/003 ,  H03K3/3565 ,  H03K5/084 ,  H04L25/063

摘要： A binarization circuit for binarizing a pulsative analog signal includes: a first comparator circuit for reversing an output signal when the analog signal becomes smaller than a threshold voltage and when the analog signal becomes larger than a high side threshold voltage; a second comparator circuit for reversing an output signal when the analog signal becomes larger than the threshold voltage and when the analog signal becomes smaller than a low side threshold voltage; and a selector circuit for inputting the output signals from the first and second comparator circuits and for reversing an output signal when the analog signal becomes smaller than the threshold voltage and when the analog signal becomes larger than the threshold voltage.

摘要翻译： 用于二值化脉冲模拟信号的二值化电路包括：第一比较器电路，用于当模拟信号变得小于阈值电压时以及当模拟信号变得大于高侧阈值电压时反转输出信号; 第二比较器电路，用于当模拟信号变得大于阈值电压时以及当模拟信号变得小于低侧阈值电压时反转输出信号; 以及选择器电路，用于输入来自第一和第二比较器电路的输出信号，并且当模拟信号变得小于阈值电压时以及当模拟信号变得大于阈值电压时反转输出信号。

公开(公告)号：US07135934B2

公开(公告)日：2006-11-14

申请号：US11069664

申请日：2005-03-01

申请人： Hector Sanchez ,  Carlos A. Greaves ,  Jim P. Nissen ,  Xinghai Tang

发明人： Hector Sanchez ,  Carlos A. Greaves ,  Jim P. Nissen ,  Xinghai Tang

IPC分类号： H03L7/089 ,  H03L7/099

CPC分类号： H03L7/0995 ,  H03K3/0377 ,  H03K5/084 ,  H03K5/133 ,  H03K2005/00071 ,  H03L7/0896

摘要： A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

摘要翻译： 包括接收器，相位频率检测器，电荷泵和VCO的可编程PLL。 接收器包括一个可编程电容分压器，用于转换输入时钟的电压以提供电平转换时钟。 AC接口包括状态检测和校正电路，其确保电平移位时钟的适当状态。 PLL包括用于产生延迟时钟控制信号的脉冲延迟调制器。 VCO包括可编程相位控制电路，其使用延迟的时钟控制信号动态调整相位。 VCO电路包括具有一个或多个相位控制节点的环形振荡器电路。 可编程相位控制电路使用时钟控制信号选择性地将设备耦合到相位控制节点以调整相位。 器件可以是电容器或晶体管，每个器件使用由延迟时钟控制信号控制的开关来切换。 电容器可以是金属电容器或半导体晶体管电容器。

公开(公告)号：US20060176082A1

公开(公告)日：2006-08-10

申请号：US11299431

申请日：2005-12-12

申请人： Colin Johnstone ,  Eric Breakenridge

发明人： Colin Johnstone ,  Eric Breakenridge

IPC分类号： G01N30/86

CPC分类号： H03K5/1252 ,  H03K5/084 ,  H03K5/1534

摘要： An apparatus and method for detecting leading pulse edges of a signal includes a controller, hysteresis threshold comparators and qualification timers. The controller uses the outputs from the timers in order to determine whether or not a transition of the input signal constitutes a leading pulse edge of the input signal.

摘要翻译： 用于检测信号的引导脉冲沿的装置和方法包括控制器，滞后阈值比较器和限定定时器。 控制器使用来自定时器的输出来确定输入信号的转换是否构成输入信号的前导脉冲沿。

公开(公告)号：US06957278B1

公开(公告)日：2005-10-18

申请号：US09605311

申请日：2000-06-28

申请人： Kevin J. Gallagher ,  Gerald D. Murphy ,  Anthony G. Dunne

发明人： Kevin J. Gallagher ,  Gerald D. Murphy ,  Anthony G. Dunne

IPC分类号： G06F13/00 ,  H03K5/08 ,  H03K5/153 ,  H03K5/24

CPC分类号： H03K5/084 ,  H03K5/2481 ,  H03K5/249

摘要： The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a reference output voltage in response to a plurality of reference voltages. The second circuit may be configured to generate an output voltage in response to the reference output voltage and an unknown voltage. The output voltage may comprise accurately controlled hysteresis.

摘要翻译： 本发明涉及包括第一电路和第二电路的装置。 第一电路可以被配置为响应于多个参考电压而产生参考输出电压。 第二电路可以被配置为响应于参考输出电压和未知电压而产生输出电压。 输出电压可以包括精确控制的滞后。

公开(公告)号：US06570934B1

公开(公告)日：2003-05-27

申请号：US09454913

申请日：1999-12-06

申请人： Kanji Harada

发明人： Kanji Harada

IPC分类号： H03K900

CPC分类号： H04L25/0292 ,  H03K3/013 ,  H03K3/0377 ,  H03K5/084 ,  H04L25/0272

摘要： An object of the invention is to prevent an erroneous operation of the internal circuits due to glitches and to dispense with a circuit as a countermeasure against glitches. There are provided a low-value threshold detector, a high-value threshold detector, and a set/reset latch circuit. The low-value threshold detector receives two differential data input DATA+ and DATA− signals and detects whether both input signals are lower than a first threshold voltage. The high-value threshold detector receives the input DATA+ and DATA− signals and detects whether one of the input signals is higher than a second threshold voltage. And the set/reset latch circuit is used for outputting an SE0 signal. the set/reset latch circuit is set when the levels of both input DATA+ and DATA− signals are lower than or equal to the first threshold voltage, and is reset when one of the levels of the input DATA+ and DATA− signals is higher than or equal to the second threshold voltage.

摘要翻译： 本发明的目的是防止由于毛刺引起的内部电路的错误操作，并且省略了电路作为防止毛刺的对策。 提供了低值阈值检测器，高值阈值检测器和设置/复位锁存电路。 低值阈值检测器接收两个差分数据输入DATA +和DATA-信号，并检测输入信号是否低于第一阈值电压。 高值阈值检测器接收输入的DATA +和DATA-信号，并检测输入信号中的一个是否高于第二阈值电压。 并且设置/复位锁存电路用于输出SE0信号。 当输入DATA +和DATA-信号的电平都低于或等于第一阈值电压时，置位/复位锁存电路被置位，并且当输入DATA +和DATA-信号的一个电平高于或等于第一阈值电压时复位， 等于第二阈值电压。

公开(公告)号：US06349121B1

公开(公告)日：2002-02-19

申请号：US09525789

申请日：2000-03-15

申请人： Jason R. Anderson

发明人： Jason R. Anderson

IPC分类号： H04L2506

CPC分类号： H03K5/084 ,  H04L25/061

摘要： A DC-coupled data slicer operates on a baseband signal based on a variable threshold and an AC-coupled data slicer operates on the baseband signal based on a fixed threshold. The variable threshold is initially set to a stored threshold value corresponding to a previously used value of the variable threshold. Differences between DC-coupled sliced data and the AC-coupled sliced data are determined and used to adjust the variable threshold. In one embodiment, the AC-coupled data slicer is characterized by a settling time constant. The variable threshold is not adjusted until expiration of a predetermined delay preferably set to be a multiple of the settling time constant. After expiry of the predetermined delay, adjustments to the variable threshold are made to correct any detected variances in the expected duty cycle of the DC-coupled data slicer output. In this manner, the present invention overcomes the problems resulting from settling times inherent in prior art techniques.

摘要翻译： DC耦合数据限幅器基于可变阈值对基带信号进行操作，并且AC耦合数据限幅器基于固定阈值对基带信号进行操作。 可变阈值最初设置为与先前使用的可变阈值的值对应的存储的阈值。 确定直流耦合切片数据与AC耦合切片数据之间的差异，并用于调整可变阈值。 在一个实施例中，AC耦合数据限幅器的特征在于稳定时间常数。 在预定延迟期满之前，可变阈值不被调整，优选设定为稳定时间常数的倍数。 在预定延迟期满之后，进行对可变阈值的调整以校正DC耦合数据限幅器输出的预期占空比中的任何检测到的方差。 以这种方式，本发明克服了现有技术中固有的沉降时间产生的问题。