公开(公告)号：US5086018A

公开(公告)日：1992-02-04

申请号：US694719

申请日：1991-05-02

Applicant: H. Ward Conru ,  Gary H. Irish ,  Francis J. Pakulski ,  William J. Slattery ,  Stephen G. Starr ,  William C. Ward

Inventor： H. Ward Conru ,  Gary H. Irish ,  Francis J. Pakulski ,  William J. Slattery ,  Stephen G. Starr ,  William C. Ward

IPC: H01L21/60 ,  H01L21/56 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L24/32 ,  H01L21/56 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/06 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/73215 ,  H01L2224/85909 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2225/06596 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253

Abstract: A method of making a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires. The insulating layer is a thermosetting adhesive and is placed over the lead frame, the bonding wires and the active face of the semiconductor chip so that when a lamination force is applied to the insulating layer the wires will be crushed and held against their respective pads and against the respective leads to which they are connected and the active face of the semiconductor protected by the adhesive bonding thereto. In this way greater contact between the wires and the leads is enhanced and defects or failure in conductivity therebetween reduced or eliminated.

Abstract translation: 一种制造半导体芯片的方法，其中可以容易且可再现地改善芯片和引线框架之间的导线通过导线。 这是通过改善导线与引线框架构件之间的接合而实现的，并且通过在每个导线与其相应引线之间产生附加的接触，即使接合的接触在接合点处或紧邻接合点处断裂或失效。 这通过在每个芯片的有源表面上放置绝缘层来实现，该绝缘层在其上承载有引线框架导体已经通过接合线连接的输入和输出接合焊盘。 绝缘层是热固性粘合剂，并且放置在引线框架，接合线和半导体芯片的有源面之上，使得当层压力施加到绝缘层时，电线将被压碎并保持抵靠它们各自的焊盘，并且 抵靠它们连接的各个引线，并且被粘合剂保护的半导体的有源面与其结合。 以这种方式，电线和引线之间的更大的接触增强，并且导电性的缺陷或故障减少或消除。

公开(公告)号：US5151559A

公开(公告)日：1992-09-29

申请号：US805214

申请日：1991-12-11

Applicant: H. Ward Conru ,  Gary H. Irish ,  Francis J. Pakulski ,  William J. Slattery ,  Stephen G. Starr ,  William C. Ward

Inventor： H. Ward Conru ,  Gary H. Irish ,  Francis J. Pakulski ,  William J. Slattery ,  Stephen G. Starr ,  William C. Ward

IPC: H01L21/56 ,  H01L23/495 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L21/56 ,  H01L23/4951 ,  H01L25/0657 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2225/06596 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253

Abstract: This is a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires. The insulating layer is a thermosetting adhesive and is placed over the lead frame, the bonding wires and the active face of the semiconductor chip so that when a lamination force is applied to the insulating layer the wires will be crushed and held against their respective pads and against the respective leads to which they are connected and the active face of the semiconductor protected by the adhesive bonding thereto. In this way greater contact between the wires and the leads is enhanced and defects or failure in conductivity therebetween reduced or eliminated.

Abstract translation: 这是一种半导体芯片，其中可以容易且可再生地改善芯片和引线框架之间通过导线的导电路径。 这是通过改善导线与引线框架构件之间的接合而实现的，并且通过在每个导线与其相应引线之间产生附加的接触，即使接合的接触在接合点处或紧邻接合点处断裂或失效。 这通过在每个芯片的有源表面上放置绝缘层来实现，该绝缘层在其上承载有引线框架导体已经通过接合线连接的输入和输出接合焊盘。 绝缘层是热固性粘合剂，并且放置在引线框架，接合线和半导体芯片的有源面之上，使得当层压力施加到绝缘层时，电线将被压碎并保持抵靠它们各自的焊盘，并且 抵靠它们连接的各个引线，并且被粘合剂保护的半导体的有源面与其结合。 以这种方式，电线和引线之间的更大的接触增强，并且导电性的缺陷或故障减少或消除。

公开(公告)号：US4761332A

公开(公告)日：1988-08-02

申请号：US937265

申请日：1987-02-24

Applicant: Kenneth L. Elias ,  Stuart R. Martin ,  William J. Slattery

Inventor： Kenneth L. Elias ,  Stuart R. Martin ,  William J. Slattery

IPC: C04B41/45 ,  H05K1/03 ,  H05K3/00 ,  B32B18/00 ,  B32B9/00 ,  B32B19/00

CPC classification number: C04B41/4572 ,  H05K1/0306 ,  H05K3/0011 ,  Y10T428/252 ,  Y10T428/259 ,  Y10T428/2993

Abstract: A method of planarizing or smoothing the surface of a ceramic substrate by deposition of a silicon nitride layer. The silicon nitride in addition to planarizing the surface forms an alpha particle barrier. The substrates suitable for planarization with silicon nitride in accordance with the method of the present invention are sintered oxide particles which are bonded with a silicon bonding phase. The silicon content of the silicon bonding phase is greater than the silicon content of the aggregate of the oxide particles. The silicon nitride is preferably deposited by plasma enhanced chemical vapor deposition, and the silicon bonding phase is preferably a glass.

Abstract translation: 通过沉积氮化硅层来平坦化或平滑陶瓷衬底的表面的方法。 除了平坦化表面之外，氮化硅形成α粒子屏障。 根据本发明的方法适用于与氮化硅平面化的衬底是与硅键合相结合的烧结氧化物颗粒。 硅键合相的硅含量大于氧化物颗粒的聚集体的硅含量。 优选通过等离子体增强化学气相沉积来沉积氮化硅，并且硅键合相优选是玻璃。

公开(公告)号：US4659585A

公开(公告)日：1987-04-21

申请号：US747598

申请日：1985-06-24

Applicant: Kenneth L. Elias ,  Stuart R. Martin ,  William J. Slattery

Inventor： Kenneth L. Elias ,  Stuart R. Martin ,  William J. Slattery

IPC: C04B41/87 ,  C04B41/45 ,  H05K1/03 ,  H05K3/00 ,  B05D3/06

CPC classification number: C04B41/4572 ,  H05K1/0306 ,  H05K3/0011

Abstract: A method of planarizing or smoothing the surface of a ceramic substrate by deposition of a silicon nitride layer. The silicon nitride in addition to planarizing the surface forms an alpha particle barrier. The substrates suitable for planarization with silicon nitride in accordance with the method of the present invention are sintered oxide particles which are bonded with a silicon bonding phase. The silicon content of the silicon bonding phase is greater than the silicon content of the aggregate of the oxide particles. The silicon nitride is preferably deposited by plasma enhanced chemical vapor deposition, and the silicon bonding phase is preferably a glass.