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公开(公告)号：US20100314713A1
公开(公告)日：2010-12-16
申请号：US12516301
申请日：2009-03-18
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.
摘要翻译： 提供了一种IC电感器结构，其包括形成在半导体衬底上的第一电感器元件和形成在靠近第一电感器元件的半导体衬底上的至少第二电感器元件。 第一电感器元件具有与其相关联的第一有效磁场方向，并且第二电感器元件具有与其相关联的第二有效磁场方向。 第一和第二电感器元件相对于彼此定向，以便在第一和第二有效磁场方向之间产生非零角度。
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公开(公告)号：US07839965B2
公开(公告)日：2010-11-23
申请号：US11602275
申请日：2006-11-21
IPC分类号： H04L7/00
CPC分类号： H04L7/0091 , H03L7/1976
摘要： A clock generator is provided for a transmitter in a transceiver adapted to communicate data over a serial data link. The transceiver includes a clock data recovery circuit recovers a receive clock signal and outputs a reference clock signal. The clock generator includes a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock outputs a local clock signal. The frequency difference detector outputs a fractional frequency difference signal based on a frequency difference between the local clock signal and the reference clock signal. The fractional-N frequency synthesizer outputs a transmit clock signal having a same frequency as the recovered receive clock signal.
摘要翻译： 为适用于通过串行数据链路传送数据的收发器中的发射机提供时钟发生器。 收发器包括时钟数据恢复电路恢复接收时钟信号并输出参考时钟信号。 时钟发生器包括本地时钟，频率差检测器和分数N频率合成器。 本地时钟输出本地时钟信号。 频差检测器基于本地时钟信号和参考时钟信号之间的频率差输出小数频差信号。 分数N频率合成器输出具有与恢复的接收时钟信号相同频率的发送时钟信号。
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公开(公告)号：US07710170B2
公开(公告)日：2010-05-04
申请号：US11928366
申请日：2007-10-30
IPC分类号： H03L7/06
摘要： Various embodiments of the present invention provide systems and circuits for clock signal generation. For example, various embodiments of the present invention provide semiconductor devices that include a power source and a phase lock loop circuit. The power source provides a supply voltage to the phase lock loop circuit. The phase lock loop circuit includes and on-chip control voltage source and a voltage controlled oscillator. The on-chip control voltage source is capable of producing a control voltage that varies between a minimum voltage and a maximum voltage. The voltage controlled oscillator receives the control voltage and provides a clock signal with a frequency corresponding to the control voltage. The maximum voltage is greater than the supply voltage. For example, in some embodiments of the present invention, the maximum voltage is more than double the supply voltage. As another example, in some embodiments of the present invention, the maximum voltage is more than six times the supply voltage.
摘要翻译： 本发明的各种实施例提供用于时钟信号产生的系统和电路。 例如，本发明的各种实施例提供了包括电源和锁相环电路的半导体器件。 电源为锁相环电路提供电源电压。 锁相环电路包括片上控制电压源和压控振荡器。 片上控制电压源能够产生在最小电压和最大电压之间变化的控制电压。 压控振荡器接收控制电压并提供具有对应于控制电压的频率的时钟信号。 最大电压大于电源电压。 例如，在本发明的一些实施例中，最大电压是电源电压的两倍。 作为另一个例子，在本发明的一些实施例中，最大电压是电源电压的六倍以上。
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公开(公告)号：US20080080656A1
公开(公告)日：2008-04-03
申请号：US11540481
申请日：2006-09-28
申请人： William B. Wilson , Mark Trafford
发明人： William B. Wilson , Mark Trafford
IPC分类号： H03D3/24
CPC分类号： H04L7/0337 , H03L7/091 , H03L7/093
摘要： Various apparatus and methods for related to clock recovery are disclosed. For example, in one illustrative embodiment, a clock recovery circuit includes a coding circuit adapted to translate a stream of first digital numbers derived from a source signal into a stream of first binary numbers and a stream of second binary numbers, a digital-to-analog converter (DAC) circuit coupled to the coding circuit and configured to provide an analog output based on the streams of first and second binary numbers and a voltage-controlled oscillator (VCO) controlled by the analog output of the DAC circuit and adapted to produce a base clock having a base clock frequency.
摘要翻译： 公开了与时钟恢复相关的各种装置和方法。 例如，在一个说明性实施例中，时钟恢复电路包括编码电路，其适于将从源信号导出的第一数字数字流转换成第一二进制数字流和第二二进制数字流，数字 - 模拟转换器（DAC）电路，其耦合到所述编码电路并且被配置为基于所述第一和第二二进制数的流提供模拟输出，以及由所述DAC电路的模拟输出控制的压控振荡器（VCO），并且适于产生 具有基本时钟频率的基本时钟。
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公开(公告)号：US07106107B2
公开(公告)日：2006-09-12
申请号：US11047388
申请日：2005-01-31
IPC分类号： H03K5/22
CPC分类号： H03K3/02337 , H03K3/3565
摘要： A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal. A hysteresis circuit is included in the comparator circuit for selectively controlling a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator. The comparator circuit includes a voltage clamp operative to limit a voltage applied to one or more devices in the control circuit, the comparator, and/or the hysteresis circuit to less than the second voltage.
摘要翻译： 比较器电路包括连接到提供第一电压的第一源的参考发生器。 参考发生器用于产生参考信号并且包括响应于第一控制信号选择性地以至少第一模式或第二模式操作的控制电路，其中在第一模式中不产生参考信号，并且在 第二模式，参考发生器用于产生参考信号。 比较器电路还包括连接到提供第二电压的第二源的比较器，第二电压小于第一电压。 比较器用于接收参考信号和输入信号，并且产生作为输入信号和参考信号之间的比较的函数的输出信号。 比较器电路中包括滞后电路，用于根据比较器的输出信号选择性地控制比较器相对于输入信号的切换阈值。 比较器电路包括电压钳位器，用于将施加到控制电路，比较器和/或滞后电路中的一个或多个器件的电压限制为小于第二电压。
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公开(公告)号：US6040742A
公开(公告)日：2000-03-21
申请号：US144913
申请日：1998-09-01
申请人： James A. Bailey , William B. Wilson
发明人： James A. Bailey , William B. Wilson
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/0898 , H04L7/033
摘要： A phase-locked loop (PLL) has a phase detector (PD), a charge pump, a loop filter, and a voltage-controlled oscillator (VCO). The PD generates DOWN pulses based on differences in phase between an input signal and a feedback signal. The charge pump has an UP current source that generates a DC UP current and a DOWN current source that generates a DOWN current based on the DOWN pulses received from the phase detector. The charge pump generates a charge-pump current based on the DC UP current and the DOWN current. The loop filter receives the charge-pump current and generates a loop-filter voltage based on a net accumulation of charge from the charge-pump current. The VCO receives the loop-filter voltage and generates an output signal whose frequency is based on the loop-filter voltage, wherein the feedback signal is generated from the output signal. By using a DC UP current source, the PLLs of the present invention are able to operate at higher frequencies than conventional charge-pump PLLs, since the UP current source in the charge pump of a conventional PLL responds less quickly to PD pulses than does a conventional DOWN current source, due to mobility differences between holes and electrons, e.g., in conventional CMOS circuitry.
摘要翻译： 锁相环（PLL）具有相位检测器（PD），电荷泵，环路滤波器和压控振荡器（VCO）。 基于输入信号和反馈信号之间的相位差，PD产生DOWN脉冲。 电荷泵具有UP电流源，其产生基于从相位检测器接收的DOWN脉冲产生DOWN电流的DC UP电流和DOWN电流源。 电荷泵基于DC UP电流和DOWN电流产生电荷泵电流。 环路滤波器接收电荷泵电流，并且基于来自电荷泵电流的电荷的净累积产生环路滤波器电压。 VCO接收环路滤波器电压并产生其频率基于环路滤波器电压的输出信号，其中从输出信号产生反馈信号。 通过使用DC UP电流源，本发明的PLL能够以比常规电荷泵PLL更高的频率工作，因为常规PLL的电荷泵中的UP电流源对PD脉冲的响应不如 常规的DOWN电流源，由于空穴和电子之间的迁移率差异，例如在常规CMOS电路中。
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公开(公告)号：USD265524S
公开(公告)日：1982-07-27
申请号：US182063
申请日：1980-08-28
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8.发明授权Method and apparatus for generating early or late sampling clocks for CDR data recovery 有权用于生成用于CDR数据恢复的早期或晚期采样时钟的方法和装置公开(公告)号：US08407511B2
公开(公告)日：2013-03-26
申请号：US12199904
申请日：2008-08-28
CPC分类号： H04L7/0337
摘要： Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.
摘要翻译： 提供了用于CDR数据采样的时钟相位发生器的方法和装置，其相对于理想的转换和采样点产生早和/或晚的采样时钟。 通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生早期采样时钟; 以及延迟所述转换时钟信号中的至少一个以产生一个或多个早期时钟信号。 通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生延迟采样时钟; 以及延迟所述数据采样时钟信号中的至少一个以产生一个或多个后期时钟信号。 早期的时钟信号可以用于例如基于阈值的判决反馈均衡器中。 后期时钟信号可以用于例如经典的判决反馈均衡器中。
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9.发明授权Method and apparatus for generation of asynchronous clock for spread spectrum transmission 有权用于产生扩频传输的异步时钟的方法和装置公开(公告)号：US07787515B2
公开(公告)日：2010-08-31
申请号：US11353431
申请日：2006-02-14
申请人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , William B. Wilson , Craig B. Ziemer
发明人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , William B. Wilson , Craig B. Ziemer
IPC分类号： H04B1/00
CPC分类号： H04L27/0014 , H04B1/7075 , H04L2027/0036
摘要： A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.
摘要翻译： 用于扩频率控制的电路使用第一内插器在第一信号和第二信号之间进行相位插值，并且基于第一控制信号产生第一输出信号。 第二内插器用于在第三信号和第四信号之间进行相位插值，并且基于第二控制信号产生第二输出信号。 多路复用器用于基于选择信号选择第一输出信号或第二输出信号作为扩频时钟（SSCLK）。 跳跃内插器控制用于与SSCLK同步地产生基于第一类型的相位调整请求的第一控制信号，基于第二类型的相位调整请求的第二控制信号，以及选择信号 在改变第一控制信号或第二控制信号之后允许内插器稳定时间之后，在第一输出信号和第二输出信号之间切换多路复用器。
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公开(公告)号：US07680217B2
公开(公告)日：2010-03-16
申请号：US11540481
申请日：2006-09-28
申请人： William B. Wilson , Mark Trafford
发明人： William B. Wilson , Mark Trafford
IPC分类号： H04L27/00
CPC分类号： H04L7/0337 , H03L7/091 , H03L7/093
摘要： Various apparatus and methods for related to clock recovery are disclosed. For example, in one illustrative embodiment, a clock recovery circuit includes a coding circuit adapted to translate a stream of first digital numbers derived from a source signal into a stream of first binary numbers and a stream of second binary numbers, a digital-to-analog converter (DAC) circuit coupled to the coding circuit and configured to provide an analog output based on the streams of first and second binary numbers and a voltage-controlled oscillator (VCO) controlled by the analog output of the DAC circuit and adapted to produce a base clock having a base clock frequency.
摘要翻译： 公开了与时钟恢复相关的各种装置和方法。 例如，在一个说明性实施例中，时钟恢复电路包括编码电路，其适于将从源信号导出的第一数字数字流转换成第一二进制数字流和第二二进制数字流，数字 - 模拟转换器（DAC）电路，其耦合到所述编码电路并且被配置为基于所述第一和第二二进制数的流提供模拟输出，以及由所述DAC电路的模拟输出控制的压控振荡器（VCO），并且适于产生 具有基本时钟频率的基本时钟。
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