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1.发明授权Method and apparatus for generating early or late sampling clocks for CDR data recovery 有权用于生成用于CDR数据恢复的早期或晚期采样时钟的方法和装置公开(公告)号：US08407511B2
公开(公告)日：2013-03-26
申请号：US12199904
申请日：2008-08-28
CPC分类号： H04L7/0337
摘要： Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.
摘要翻译： 提供了用于CDR数据采样的时钟相位发生器的方法和装置，其相对于理想的转换和采样点产生早和/或晚的采样时钟。 通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生早期采样时钟; 以及延迟所述转换时钟信号中的至少一个以产生一个或多个早期时钟信号。 通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生延迟采样时钟; 以及延迟所述数据采样时钟信号中的至少一个以产生一个或多个后期时钟信号。 早期的时钟信号可以用于例如基于阈值的判决反馈均衡器中。 后期时钟信号可以用于例如经典的判决反馈均衡器中。
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公开(公告)号：US08315298B2
公开(公告)日：2012-11-20
申请号：US11930780
申请日：2007-10-31
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/0262 , H04L2025/03547
摘要： Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).
摘要翻译： 提供了用于均衡接收信号的方法和装置。 接收到的信号通过确定接收信号的数据速率来均衡; 获得与所确定的数据速率相关联的一个或多个均衡参数; 以及使用所获得的一个或多个均衡参数来均衡所接收的信号。 均衡参数可以包括例如增益参数，高通滤波器的零控制和在均衡步骤期间使用的一个或多个锁存器的一个或多个阈值设置中的一个或多个，诸如数据锁存器或转换锁存器（或 都）。
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3.发明授权Methods and apparatus for detecting a loss of lock condition in a clock and data recovery system 有权用于检测时钟和数据恢复系统中锁定状况的损失的方法和装置公开(公告)号：US08208521B2
公开(公告)日：2012-06-26
申请号：US11967632
申请日：2007-12-31
IPC分类号： H04B17/00
CPC分类号： H04L7/0062 , H04L7/0083
摘要： Methods and apparatus are provided for detecting a loss of lock condition in a clock and data recovery system. A loss of lock condition is detected in a clock and data recovery system that generates a recovered clock signal from a received signal by sampling the received signal for a plurality of different phases using one or more latches clocked by the recovered clock; evaluating the samples to monitor a data eye associated with the received signal; and detecting the loss of lock condition if the data eye does not satisfy one or more predefined conditions. Generally, the predefined conditions identify a loss of the data eye (e.g., when the data eye cannot be substantially detected), for example, based on a degree of opening of the data eye. The clock and data recovery system can optionally be restarted if the loss of lock condition is detected.
摘要翻译： 提供了用于检测时钟和数据恢复系统中的锁定状况的损失的方法和装置。 在时钟和数据恢复系统中检测到锁定状态的损失，该系统通过使用由恢复时钟计时的一个或多个锁存器对接收到的信号进行多个不同相位的采样来产生来自接收信号的恢复时钟信号; 评估样本以监测与接收信号相关联的数据眼; 并且如果数据眼不满足一个或多个预定条件，则检测锁定条件的损失。 通常，预定义的条件识别数据眼睛的损失（例如，当不能基本上检测到数据眼时），例如，基于数据眼睛的打开程度。 如果检测到锁定状态的丢失，则可以重新启动时钟和数据恢复系统。
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4.发明授权Method and apparatus for decision-feedback equalization using single-sided eye with global minimum convergence 有权使用具有全局最小收敛的单面眼的判决反馈均衡的方法和装置公开(公告)号：US07720142B2
公开(公告)日：2010-05-18
申请号：US11686148
申请日：2007-03-14
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： Methods and apparatus are provided for decision-feedback equalization with global minimum convergence. A threshold position of one or more DFE latches employed by a decision-feedback equalizer is determined by obtaining a plurality of samples of a single-sided data eye using at least one decision latch and at least one roaming latch; comparing the samples obtained by the at least one decision latch and at least one roaming latch to identify an upper and lower voltage boundary of the single-sided data eye; and determining a threshold position of the one or more DFE latches based on the upper and lower voltage boundaries. The comparison can optionally comprise obtaining an exclusive or (XOR) of the samples obtained by the at least one decision latch and at least one roaming latch. The XOR comparison positions an opening for the single-sided data eye at a zero hit count.
摘要翻译： 提供了用于具有全局最小收敛的判决反馈均衡的方法和装置。 通过使用至少一个判定锁存器和至少一个漫游锁存器获得单面数据眼睛的多个采样来确定由判决反馈均衡器采用的一个或多个DFE锁存器的阈值位置; 将由所述至少一个判定锁存器获得的样本和至少一个漫游锁存器进行比较，以识别所述单侧数据眼睛的上下电压边界; 以及基于所述上下电压边界确定所述一个或多个DFE锁存器的阈值位置。 比较可以可选地包括获得由至少一个决定锁存器和至少一个漫游锁存器获得的样本的异或（XOR）。 XOR比较将零点击数的单面数据眼的开口位置。
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5.发明授权Method and apparatus for non-linear decision-feedback equalization in the presence of asymmetric channel 有权在存在非对称信道的情况下进行非线性判决反馈均衡的方法和装置公开(公告)号：US07606302B2
公开(公告)日：2009-10-20
申请号：US11541379
申请日：2006-09-29
CPC分类号： H04L25/03057 , H04B10/695
摘要： Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization in the presence of a non-linear channel. A latch employed by a decision-feedback equalizer is positioned by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; determining a threshold position of the latch based on the samples; and transforming the determined position to address the non-linearity of the channel. For example, a non-linear mapping table can map measured threshold values to transformed threshold values based on distance.
摘要翻译： 提供了用于在存在非线性通道的情况下确定用于判决反馈均衡的一个或多个锁存器的阈值位置的方法和装置。 由判决反馈均衡器采用的锁存器通过约束输入数据来定位，使得输入数据仅包含来自第一二进制值的转换; 获得与所述约束输入数据相关联的单面数据眼睛的多个样本; 基于所述样本确定所述锁存器的阈值位置; 并且变换确定的位置以解决信道的非线性。 例如，非线性映射表可以将测量的阈值映射到基于距离的变换的阈值。
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6.发明申请公开(公告)号：US20080225734A1
公开(公告)日：2008-09-18
申请号：US11686144
申请日：2007-03-14
IPC分类号： H04J1/16
CPC分类号： H04L25/0262
摘要： Methods and apparatus are provided for data rate detection using a data eye monitor. The data rate is one of a plurality of data rates comprising a base rate and one or more divide-by-N multiples of the base rate, where N is an integer. The data rate of a received signal is detected by sampling the received signal; comparing the samples for a plurality of full rate data eyes associated with the received signal to determine if there is a mismatch between at least two predefined samples; and detecting the data rate by evaluating the comparison based on predefined criteria. The comparison can be performed by an exclusive or (XOR) logic gate for samples of at least two adjacent data eyes of a given rate.
摘要翻译： 提供了使用数据眼监视器进行数据速率检测的方法和装置。 数据速率是包括基本速率和基本速率的一个或多个除以N倍数的多个数据速率之一，其中N是整数。 通过对接收到的信号进行采样来检测接收信号的数据速率; 比较与所接收的信号相关联的多个全速率数据眼睛的样本，以确定是否存在至少两个预定样本之间的不匹配; 以及通过基于预定标准评估比较来检测数据速率。 可以通过异或（XOR）逻辑门对给定速率的至少两个相邻数据眼的样本执行比较。
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公开(公告)号：US4783657A
公开(公告)日：1988-11-08
申请号：US828103
申请日：1986-02-10
IPC分类号： G06F15/173 , H04Q9/00 , H04Q11/00
CPC分类号： G06F15/17337 , G06F15/17368
摘要： In a processor intercommunication network, every pair of processors is connected by a separate path for carrying multi-bit orders so that in an N processor multiprocessing system there are N-1 bidirectional communication paths to and from each of the N processors. To send an order from one processor to another processor each of the N processors has a routing circuit to select the proper path to that other processor. The routing circuit compares the sender's own address to the address of the intended receiver to select the appropriate sending path. Each of the N processors also has a receiving circuit to block orders from any one of the other processors. In blocking orders, these receiving circuits use the receiver's address to determine which one of the N-1 paths is from that of any one processor.
摘要翻译： 在处理器互通网络中，每对处理器通过用于承载多位命令的单独路径连接，使得在N个处理器多处理系统中存在N个到每个处理器的N-1个双向通信路径。 为了将订单从一个处理器发送到另一个处理器，每个N个处理器都有一个路由电路，以选择到另一个处理器的正确路径。 路由电路将发送者自己的地址与预期接收者的地址进行比较，以选择适当的发送路径。 N个处理器中的每一个还具有一个接收电路，以阻止任何一个其他处理器的命令。 在阻塞顺序中，这些接收电路使用接收器的地址来确定N-1路径中的哪一个来自任何一个处理器。
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8.发明授权公开(公告)号：US08320439B2
公开(公告)日：2012-11-27
申请号：US12040575
申请日：2008-02-29
IPC分类号： H03H7/30
CPC分类号： H04L25/03006 , H04L25/03343 , H04L2025/0377 , H04L2025/03808
摘要： Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one or more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver. The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern Noise margins and jitters margins for the channel can optionally be improved.
摘要翻译： 为自适应链路伙伴发射机均衡提供了方法和装置。 根据本发明的一个方面，本地收发器通过在链路伙伴和本地收发信机之间的信道上接收训练帧来适配链路伙伴的一个或多个均衡参数，其中训练帧由预定义的训练模式组成; 调整所述链路伙伴的一个或多个均衡参数; 以及基于所述本地收发器是否适当地接收了所述预定训练模式，确定所述信道的均衡是否满足一个或多个预定标准。 预定义的训练模式可以是伪随机模式，例如PN11模式，可以可选地提高通道的噪声余量和抖动余量。
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公开(公告)号：US20100237915A1
公开(公告)日：2010-09-23
申请号：US12789544
申请日：2010-05-28
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the deter wined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译： 提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 电压控制延迟环可以使用阻尼控制信号启动。 可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。
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10.发明申请Methods and Apparatus for Improved Jitter Tolerance in an SFP Limit Amplified Signal 失效用于改善SFP限幅放大信号中抖动容限的方法和装置公开(公告)号：US20090168940A1
公开(公告)日：2009-07-02
申请号：US11967602
申请日：2007-12-31
申请人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
发明人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
IPC分类号： H04L7/00
CPC分类号： H04B10/6972
摘要： Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.
摘要翻译： 提供了用于改善SFP限幅放大信号中的抖动容限的方法和装置。 在通信接收机中通过将接收到的信号施加到SFP限幅放大器来提高抖动容差; 并将SFP限幅放大器的输出施加到低通滤波器以提高抖动容限。 低通滤波器可选择地将可编程量的衰减应用于输出的高频分量。 低通滤波器转换速率控制（即旋转）接收信号的数据眼表示，以沿着时间轴增加数据眼睛表示。 可以通过将低通滤波器的输出施加到全通滤波器来可选地改善接收信号的噪声容限。 压摆率控制器可以评估数据眼统计量，以确定低通滤波器的设置。
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