公开(公告)号：US08008144B2

公开(公告)日：2011-08-30

申请号：US11432270

申请日：2006-05-11

申请人： Venkatesan Ananthan ,  Sanh D. Tang

发明人： Venkatesan Ananthan ,  Sanh D. Tang

IPC分类号： H01L29/94

CPC分类号： H01L29/7827 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66621

摘要： A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device.

摘要翻译： 具有由具有不同功函数的两个或多个栅极材料形成的栅电极的凹陷存取装置可以减小来自凹陷存取装置的栅极引起的漏极漏电流损耗。 栅电极可以包括具有设置在凹陷入口装置的底部中的高功函的第一栅极材料和具有设置在第一栅极材料上的下功函数的第二栅极材料以及凹陷入口装置的上部 。

公开(公告)号：US08501581B2

公开(公告)日：2013-08-06

申请号：US11393513

申请日：2006-03-29

申请人： Sanh D. Tang ,  Venkatesan Ananthan

发明人： Sanh D. Tang ,  Venkatesan Ananthan

IPC分类号： H01L21/8229

CPC分类号： H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7827 ,  H01L29/7841

摘要： The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.

摘要翻译： 本发明包括含有U形半导体材料片的浮体晶体管结构。 U形有一对连接到中心部分的插脚。 每个插脚包含一对门控耦合的源极/漏极区域的源极/漏极区域，并且晶体管的浮体在中心部分内。 半导体材料切片可以位于前门和后门之间。 可以将浮体晶体管结构并入到存储器阵列中，这又可以并入到电子系统中。 本发明还包括形成浮体晶体管结构的方法，以及将浮体晶体管结构结合到存储器阵列中的方法。

公开(公告)号：US20110042754A1

公开(公告)日：2011-02-24

申请号：US12938114

申请日：2010-11-02

申请人： D.V. Nirmal Ramaswamy ,  Venkatesan Ananthan

发明人： D.V. Nirmal Ramaswamy ,  Venkatesan Ananthan

IPC分类号： H01L29/78 ,  H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L21/823857

摘要： The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.

摘要翻译： 本发明包括形成PMOS晶体管和NMOS晶体管的方法。 NMOS晶体管可以形成为在一对金属氮化物材料之间具有薄的含硅材料，而PMOS晶体管形成为使得金属氮化物材料彼此直接相对。 本发明还包括在一对金属氮化物材料之间包含具有薄的含硅材料的NMOS晶体管栅极叠层的构造。 含硅材料可以例如由硅，导电掺杂的硅或氧化硅组成; 并且可以具有小于或等于约30埃的厚度。

公开(公告)号：US20090236657A1

公开(公告)日：2009-09-24

申请号：US12053977

申请日：2008-03-24

申请人： Venkatesan Ananthan

发明人： Venkatesan Ananthan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7827 ,  H01L29/66666 ,  H01L29/7391

摘要： Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSET devices while maintaining a footprint equal to or less than conventional MOSFET devices.

摘要翻译： 公开了包括垂直和凹陷的冲击电离金属氧化物半导体场效应晶体管（MOSFET）器件的冲击电离装置及其形成方法。 器件需要比传统MOSFET器件更低的阈值电压，同时保持等于或小于传统MOSFET器件的占空比。

公开(公告)号：US20120112272A1

公开(公告)日：2012-05-10

申请号：US13312801

申请日：2011-12-06

申请人： Venkatesan Ananthan

发明人： Venkatesan Ananthan

IPC分类号： H01L29/78 ,  H01L27/088

CPC分类号： H01L29/7827 ,  H01L21/845 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7851

摘要： A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.

摘要翻译： 在半导体材料中形成开口的方法包括在颈部下方形成颈部，圆形部分，在一些实施例中，在圆形部分下方形成突出部分。 该开口可以填充有导体，电介质或两者。 公开了形成晶体管栅极，浅沟槽隔离以及分离晶体管源极和漏极的隔离材料的实施例。 还描述了通过该方法形成的器件结构。

公开(公告)号：US20110006365A1

公开(公告)日：2011-01-13

申请号：US12877827

申请日：2010-09-08

申请人： Venkatesan Ananthan

发明人： Venkatesan Ananthan

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/845 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7851

摘要： A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.

摘要翻译： 在半导体材料中形成开口的方法包括在颈部下方形成颈部，圆形部分，在一些实施例中，在圆形部分下方形成突出部分。 该开口可以填充有导体，电介质或两者。 公开了形成晶体管栅极，浅沟槽隔离以及分离晶体管源极和漏极的隔离材料的实施例。 还描述了通过该方法形成的器件结构。

公开(公告)号：US20090206418A1

公开(公告)日：2009-08-20

申请号：US12431491

申请日：2009-04-28

申请人： D.V. Nirmal Ramaswamy ,  Venkatesan Ananthan

发明人： D.V. Nirmal Ramaswamy ,  Venkatesan Ananthan

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L21/823857

摘要： The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.

摘要翻译： 本发明包括形成PMOS晶体管和NMOS晶体管的方法。 NMOS晶体管可以形成为在一对金属氮化物材料之间具有薄的含硅材料，而PMOS晶体管形成为使得金属氮化物材料彼此直接相对。 本发明还包括在一对金属氮化物材料之间包含具有薄的含硅材料的NMOS晶体管栅极叠层的构造。 含硅材料可以例如由硅，导电掺杂的硅或氧化硅组成; 并且可以具有小于或等于约30埃的厚度。

公开(公告)号：US20070252175A1

公开(公告)日：2007-11-01

申请号：US11393513

申请日：2006-03-29

申请人： Sanh Tang ,  Venkatesan Ananthan

发明人： Sanh Tang ,  Venkatesan Ananthan

IPC分类号： H01L29/76

CPC分类号： H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7827 ,  H01L29/7841

摘要： The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.

摘要翻译： 本发明包括含有U形半导体材料片的浮体晶体管结构。 U形有一对连接到中心部分的插脚。 每个插脚包含一对门控耦合的源极/漏极区域的源极/漏极区域，并且晶体管的浮体在中心部分内。 半导体材料切片可以位于前门和后门之间。 可以将浮体晶体管结构并入到存储器阵列中，这又可以并入到电子系统中。 本发明还包括形成浮体晶体管结构的方法，以及将浮体晶体管结构结合到存储器阵列中的方法。

公开(公告)号：US08169032B2

公开(公告)日：2012-05-01

申请号：US12938114

申请日：2010-11-02

申请人： D. V. Nirmal Ramaswamy ,  Venkatesan Ananthan

发明人： D. V. Nirmal Ramaswamy ,  Venkatesan Ananthan

IPC分类号： H01L29/78 ,  H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L21/823857

摘要： The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.

摘要翻译： 本发明包括形成PMOS晶体管和NMOS晶体管的方法。 NMOS晶体管可以形成为在一对金属氮化物材料之间具有薄的含硅材料，而PMOS晶体管形成为使得金属氮化物材料彼此直接相对。 本发明还包括在一对金属氮化物材料之间包含具有薄的含硅材料的NMOS晶体管栅极叠层的构造。 含硅材料可以例如由硅，导电掺杂的硅或氧化硅组成; 并且可以具有小于或等于约30埃的厚度。

公开(公告)号：US07851869B2

公开(公告)日：2010-12-14

申请号：US12431491

申请日：2009-04-28

申请人： D. V. Nirmal Ramaswamy ,  Venkatesan Ananthan

发明人： D. V. Nirmal Ramaswamy ,  Venkatesan Ananthan

IPC分类号： H01L21/70

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L21/823857

摘要： The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.

摘要翻译： 本发明包括形成PMOS晶体管和NMOS晶体管的方法。 NMOS晶体管可以形成为在一对金属氮化物材料之间具有薄的含硅材料，而PMOS晶体管形成为使得金属氮化物材料彼此直接相对。 本发明还包括在一对金属氮化物材料之间包含具有薄的含硅材料的NMOS晶体管栅极叠层的构造。 含硅材料可以例如由硅，导电掺杂的硅或氧化硅组成; 并且可以具有小于或等于约30埃的厚度。