公开(公告)号：US20120200486A1

公开(公告)日：2012-08-09

申请号：US12931783

申请日：2011-02-09

Applicant: Walter B. Meinel ,  Kalin V. Lazarov ,  Timothy V. Kalthoff

Inventor： Walter B. Meinel ,  Kalin V. Lazarov ,  Timothy V. Kalthoff

IPC: G09G5/00

CPC classification number: G06F3/017 ,  H04N5/33

Abstract: A system for generating tracking coordinate information in response to movement of an information-indicating element includes an array (55) of IR sensors (60-x,y) disposed along a surface (55A) of the array. Each IR sensor includes first (7) and second (8) thermopile junctions connected in series to form a thermopile (7,8) within a dielectric stack (3) of a radiation sensor chip (1). The first thermopile junction is more thermally insulated from a substrate (2) of the radiation sensor chip than the second thermopile junction. A sensor output signal between the first and second thermopile junctions is coupled to a bus (63). A processing device (64) is coupled to the bus for operating on information representing temperature differences between the first and second thermopile junctions of the various IR sensors, respectively, caused by the presence of the information-indicating element to produce the tracking coordinate information as the information-indicating element moves along the surface.

Abstract translation: 用于响应于信息指示元件的移动产生跟踪坐标信息的系统包括沿阵列的表面（55A）设置的IR传感器（60-x，y）的阵列（55）。 每个IR传感器包括串联连接的第一（7）和第二（8）热电堆接头，以在辐射传感器芯片（1）的介质堆叠（3）内形成热电堆（7,8）。 与第二热电堆连接点相比，第一热电堆结与辐射传感器芯片的基板（2）更加热绝缘。 第一和第二热电堆之间的传感器输出信号耦合到总线（63）。 处理装置（64）被耦合到总线，用于对表示各种IR传感器的第一和第二热电堆之间的温差的信息分别进行操作，这是由信息指示元件的存在引起的，以产生跟踪坐标信息， 信息指示元件沿表面移动。

公开(公告)号：US20110181258A1

公开(公告)日：2011-07-28

申请号：US12657543

申请日：2010-01-22

Applicant: Vadim V. Ivanov ,  Timothy V. Kalthoff

Inventor： Vadim V. Ivanov ,  Timothy V. Kalthoff

IPC: G05F1/00 ,  G05F1/10

CPC classification number: G05F1/56 ,  G05F1/575

Abstract: A converter (10) for converting a first DC voltage (VDD) to a second DC voltage (VOUT) includes an output stage (40) for producing the second DC voltage (VOUT) in response to both the first DC voltage (VDD) and an output of an error amplifier (20). A sampling circuit (15) periodically energizes a voltage divider (R0,R1) by periodically coupling a first terminal thereof to the second DC voltage and periodically coupling an output (14) of the energized voltage divider to a feedback conductor (7) to refresh a feed back capacitor (C0) coupled between the second DC voltage and the feedback conductor. The feedback conductor is coupled to an input of the error amplifier.

Abstract translation: 用于将第一直流电压（VDD）转换为第二直流电压（VOUT）的A转换器（10）包括用于响应于第一直流电压（VDD）和第二直流电压（VDD）两者产生第二直流电压（VOUT）的输出级（40） 误差放大器（20）的输出。 采样电路（15）通过将其第一端周期性地耦合到第二DC电压并周期性地耦合到通电分压器的输出（14）到反馈导体（7）来周期性地激励分压器（R0，R1），以刷新 耦合在第二DC电压和反馈导体之间的反馈电容器（C0）。 反馈导体耦合到误差放大器的输入端。

公开(公告)号：US07796060B2

公开(公告)日：2010-09-14

申请号：US12188014

申请日：2008-08-07

Applicant: Ralph G. Oberhuber ,  Timothy V. Kalthoff

Inventor： Ralph G. Oberhuber ,  Timothy V. Kalthoff

IPC: H03M13/00

CPC classification number: H03M1/06 ,  H03M1/0682 ,  H03M1/682 ,  H03M1/747 ,  H03M1/765

Abstract: Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second voltage-current converter circuits, each including a first transistor and a second transistor, each having a first electrode configured to receive a signal generated by a corresponding current source, a first current source providing a signal to the first voltage-converter circuit and comprising a first error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a first current through the first current source to operate the first voltage-converter circuit in a nominal linear operating mode, and a second current source providing a signal to the second voltage-converter circuit and comprising a second error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a second current through the second current source to operate the second voltage-converter circuit in the nominal linear operating mode.

Abstract translation: 这里描述了最小化内插电路中的非线性误差的电路和方法。 公开的示例电路包括第一和第二电压 - 电流转换器电路，每个电压 - 电流转换器电路各自包括第一晶体管和第二晶体管，每个具有第一电极，第一电极被配置为接收由相应的电流源产生的信号;第一电流源， 第一电压转换器电路，并且包括第一误差校正电路，以通过设置通过第一电流源的第一电流来最小化内插电路中的积分非线性误差，以在标称线性运行模式下操作第一电压转换器电路，以及第二电流 源向第二电压转换器电路提供信号，并且包括第二误差校正电路，以通过设置通过第二电流源的第二电流来最小化内插电路中的积分非线性误差，以在额定线性运行中操作第二电压转换器电路 模式。

公开(公告)号：US5905398A

公开(公告)日：1999-05-18

申请号：US827725

申请日：1997-04-08

Applicant: James L. Todsen ,  Timothy V. Kalthoff

Inventor： James L. Todsen ,  Timothy V. Kalthoff

IPC: H03K17/693 ,  H03M1/10 ,  H03M1/12 ,  H03M1/80 ,  H03M3/02

CPC classification number: H03M1/1061 ,  H03K17/693 ,  H03M1/804

Abstract: A programmable integrated circuit capacitor array includes a plurality of binarily weighted capacitors (16) and a plurality of switches (18) selectively coupling the capacitors in parallel between first and second terminals. A control circuit (10) responds to a plurality of capacitance selection inputs (CS0,1,2) in conjunction with a plurality of trim inputs (TR0,1) and a sign input (TRS) to produce a plurality of selection signals (SEL0,1 . . . 7) on control electrodes of the switches to couple one or more of the capacitors and thereby provide an accurate value of the desired capacitance between the first and second terminals despite any manufacturing deviations in capacitance per unit area.

Abstract translation: 可编程集成电路电容器阵列包括多个二次加权电容器（16）和多个开关（18），其选择性地将电容器并联在第一和第二端子之间。 控制电路（10）结合多个调整输入（TR0,1）和符号输入（TRS）响应多个电容选择输入（CS0,1,2），以产生多个选择信号（SEL0 ，1 ... 7）连接在开关的控制电极上以耦合一个或多个电容器，从而提供第一和第二端子之间的期望电容的精确值，尽管每单位面积的电容量有任何制造偏差。

公开(公告)号：US5367302A

公开(公告)日：1994-11-22

申请号：US111113

申请日：1993-08-24

Applicant: Timothy V. Kalthoff ,  Gregory S. Waterfall

Inventor： Timothy V. Kalthoff ,  Gregory S. Waterfall

IPC: H03M1/80 ,  H03M1/50

CPC classification number: H03M1/804

Abstract: A current integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to receive a ground voltage and an inverting input coupled to an input conductor, with an input current flowing through the input conductor, an integrating capacitor having a first terminal coupled by an isolation switch to the input conductor. A reset circuit is coupled to the integrating capacitor and is operative to reset the integrating capacitor before each integrating cycle. A digital-to-analog converter, which may be a CDAC, has an output coupled to a second terminal of the integrating capacitor, which may constitute the capacitors of the CDAC. An input of a tracking circuit is coupled to an output of the comparator to produce digital signals on digital inputs of the digital-to-analog converter to maintain the input of the comparator close to a virtual ground voltage, a digital signal on the inputs of the digital-to-analog converter representing the integral of the input current. The isolation switch opens during transients occurring on a charge summing conductor during digital-to-analog converter update and reset operations. An internal reset switch is coupled between a reference conductor and the first level. An external switch is coupled between ground and the input conductor.

Abstract translation: 电流积分模数转换器包括具有耦合以接收接地电压的非反相输入和耦合到输入导体的反相输入的比较器，其中输入电流流过输入导体，积分电容器具有第一 端子通过隔离开关耦合到输入导体。 复位电路耦合到积分电容器，并且可操作以在每个积分周期之前复位积分电容器。 可以是CDAC的数/模转换器具有耦合到积分电容器的第二端子的输出，其可以构成CDAC的电容器。 跟踪电路的输入耦合到比较器的输出端，以在数/模转换器的数字输入端产生数字信号，以保持比较器的输入接近虚拟接地电压，输入端的数字信号 数模转换器表示输入电流的积分。 在数模转换器更新和复位操作期间，在充电求和导体发生瞬变期间，隔离开关打开。 内部复位开关耦合在参考导体和第一电平之间。 外部开关耦合在地和输入导体之间。

公开(公告)号：US4901031A

公开(公告)日：1990-02-13

申请号：US298116

申请日：1989-01-17

Applicant: Timothy V. Kalthoff ,  Rodney T. Burt ,  R. Mark Stitt, II

Inventor： Timothy V. Kalthoff ,  Rodney T. Burt ,  R. Mark Stitt, II

IPC: H03F3/16 ,  H03F3/45

CPC classification number: H03F3/45278 ,  H03F3/45286 ,  H03F3/4586 ,  H03F2200/372 ,  H03F2203/45302 ,  H03F2203/45304 ,  H03F2203/45394 ,  H03F2203/45674 ,  H03F2203/45702

Abstract: A common-base, source-driven differential amplifier achieves both high speed operation and low noise operation by providing an input stage including a pair of source follower JFETs that drive emitters of a pair of NPN input transistors having their bases connected together and to a bias circuit. The collectors of the NPN transistors each are connected to a corresponding load device and to a corresponding input of an output amplifier stage. The bias circuit includes a current source and a pair of diode-connected NPN transistors having their bases and collectors connected to the current source and to the bases of the input transistors. The emitters of the diode-connected NPN transistors are connected to sources of a second pair of source follower JFETs, the gates of which are connected to the input terminals.

Abstract translation: 通用基极源驱动差分放大器通过提供包括一对源极跟随器JFET的输入级来实现高速运算和低噪声运算，该对源极跟随器JFET驱动其基极连接在一起的一对NPN输入晶体管的发射极和偏置 电路。 NPN晶体管的集电极各自连接到相应的负载装置和输出放大器级的相应输入端。 偏置电路包括电流源和一对二极管连接的NPN晶体管，其基极和集电极连接到电流源和输入晶体管的基极。 二极管连接的NPN晶体管的发射极连接到第二对源极跟随器JFET的源极，其栅极连接到输入端子。

公开(公告)号：US07047263B2

公开(公告)日：2006-05-16

申请号：US09929855

申请日：2001-08-14

Applicant: James L. Todsen ,  Ka Y. Leung ,  Timothy V. Kalthoff

Inventor： James L. Todsen ,  Ka Y. Leung ,  Timothy V. Kalthoff

IPC: G06F17/17 ,  G06F17/10

CPC classification number: H03H17/0283

Abstract: A technique and circuit is provided for facilitating a faster settling time for a digital filter for use with an analog-to-digital converter. An exemplary technique utilizes a composite filter for a faster settling, lower noise resolution filter in a parallel configuration with a slower settling, higher noise resolution filter. As a result, valid data can be received faster for processing by the analog-to-digital converter. In addition, a composite digital filter circuit can include a three filter configuration including a fast-settling, low resolution first filter, a slower-settling, higher resolution second filter, and an even slower-settling, even higher resolution third filter, each of the filters configured in a parallel arrangement. Additional or fewer filters can also be provided. Moreover, the gain of each filter path can be suitably matched to the gain of any other filter path in the digital filter circuit to provide a filter output having an equalized gain regardless of the filter path selected. For example, a filter path can be suitably configured with a multiplier component such that an equalized gain can be realized for each filter path. In addition, the various filters of the digital filter circuit can be configured within the parallel arrangement to provide reduce layout requirements through the sharing of components. For example, a second filter can share at least two integrators with the third filter, and the first filter can share at least one integrator with the third filter. Further, the digital filter can be suitably configured for operation in various industrial applications. For example, the first filter can be suitably configured with a notch filter configured to replace the first, third and other odd harmonic notches of the first filter.

Abstract translation: 提供了一种技术和电路，用于促进数字滤波器与模数转换器一起使用的更快的建立时间。 一种示例性技术利用复合滤波器用于具有较慢建立的较高噪声分辨率滤波器的并行配置的更快建立的较低噪声分辨率滤波器。 因此，可以更快地接收有效数据以供模拟数字转换器处理。 此外，复合数字滤波器电路可以包括三滤波器配置，其包括快速稳定，低分辨率第一滤波器，较慢稳定的，较高分辨率的第二滤波器，以及甚至更慢稳定，甚至更高分辨率的第三滤波器， 滤波器以并联的方式配置。 还可以提供额外的或更少的过滤器。 此外，每个滤波器路径的增益可以适当地匹配数字滤波器电路中的任何其它滤波器路径的增益，以提供具有均衡增益的滤波器输出，而不管所选择的滤波器路径如何。 例如，滤波器路径可以适当地配置有乘法器组件，使得可以为每个滤波器路径实现均衡的增益。 此外，数字滤波器电路的各种滤波器可以在并行布置内配置，以通过共享组件来提供降低的布局要求。 例如，第二滤波器可以与第三滤波器共享至少两个积分器，并且第一滤波器可以与第三滤波器共享至少一个积分器。 此外，数字滤波器可以适当地构造用于在各种工业应用中操作。 例如，第一滤波器可以适当地配置有陷波滤波器，该陷波滤波器被配置为代替第一滤波器的第一，第三和其它奇数谐波陷波。

公开(公告)号：US5691720A

公开(公告)日：1997-11-25

申请号：US613112

申请日：1996-03-08

Applicant: Binan Wang ,  Timothy V. Kalthoff ,  Miaochen Wu

Inventor： Binan Wang ,  Timothy V. Kalthoff ,  Miaochen Wu

IPC: H03M3/02 ,  H03M3/00

CPC classification number: H03M3/392 ,  H03M3/374 ,  H03M3/43 ,  H03M3/454

Abstract: Programmable resolution/bias current control circuitry is provided in a delta sigma analog-to-digital converter including an input sampling circuit, a feedback reference sampling circuit, an integrator including an operational amplifier, a comparator, and a digital filter, the input sampling circuit and the feedback reference sampling circuit being coupled to a first input of the operational amplifier, an output of the operational amplifier being coupled to an input of the comparator, an output of the comparator being coupled to an input of the digital filter. The programmable resolution/bias control circuitry includes a clock generator circuit supplying a clock signal to the input sampling circuit and the feedback sampling circuit at a sampling frequency determined by a sampling frequency control signal. A bias current generator circuit supplies a bias current to the operational amplifier to control the settling time of an output step voltage signal produced by the operational amplifier. A control circuit receives a resolution control signal and changes both the sampling frequency control signal and a bias control signal in response to the resolution control signal so as to achieve a predetermined tradeoff between resolution of the digital output and dc power dissipation of the analog-to-digital converter.

Abstract translation: 可编程分辨率/偏置电流控制电路在包括输入采样电路，反馈参考采样电路，包括运算放大器，比较器和数字滤波器的积分器的Δ-Σ模数转换器中提供，输入采样电路 并且所述反馈参考采样电路耦合到所述运算放大器的第一输入，所述运算放大器的输出耦合到所述比较器的输入，所述比较器的输出耦合到所述数字滤波器的输入端。 可编程分辨率/偏置控制电路包括以采样频率控制信号确定的采样频率向输入采样电路和反馈采样电路提供时钟信号的时钟发生器电路。 偏置电流发生器电路向运算放大器提供偏置电流以控制由运算放大器产生的输出阶跃电压信号的建立时间。 控制电路接收分辨率控制信号，并响应于分辨率控制信号改变采样频率控制信号和偏置控制信号，以便实现数字输出的分辨率与模数转换器的直流功率消耗之间的预定权衡 数字转换器

公开(公告)号：US4954769A

公开(公告)日：1990-09-04

申请号：US308109

申请日：1989-02-08

Applicant: Timothy V. Kalthoff

Inventor： Timothy V. Kalthoff

IPC: H03F1/26 ,  G05F1/46 ,  G05F3/30 ,  H03F1/30 ,  H03F3/347

CPC classification number: G05F3/30 ,  G05F1/467 ,  H01L2924/0002

Abstract: A stable, low noise, low output impedance CMOS reference voltage circuit includes a CMOS/bipolar band gap circuit producing a reference voltage on the source of a source follower transistor driven by an output of a CMOS differential amplifier which maintains a V.sub.THERMAL voltage across the bases of a pair of emitter follower transistors driving the inputs of the CMOS differential amplifier. A power supply noise rejection circuit includes a cascode MOSFET coupling the drain of the source follower output transistor to a positive power supply voltage conductor. A current mirror circuit greatly attenuates any power supply voltage perturbations before they reach the gate of the cascode MOSFET. A unity gain buffer includes a CMOS differential amplifier input stage with one input coupled to the output of the source follower transistor and an output driving a CMOS operational transconductance amplifier.

Abstract translation: 稳定，低噪声，低输出阻抗CMOS参考电压电路包括CMOS /双极性带隙电路，其在由CMOS差分放大器的输出驱动的源极跟随器晶体管的源极上产生参考电压，该差分放大器在基极上保持VTHERMAL电压 的一对射极跟随器晶体管驱动CMOS差分放大器的输入。 电源噪声抑制电路包括将源极跟随器输出晶体管的漏极耦合到正电源电压导体的共源共栅MOSFET。 电流镜电路在到达共源共栅MOSFET的栅极之前会大大衰减任何电源电压扰动。 单位增益缓冲器包括CMOS差分放大器输入级，其中一个输入耦合到源极跟随器晶体管的输出端和驱动CMOS运算跨导放大器的输出。

公开(公告)号：US08581770B2

公开(公告)日：2013-11-12

申请号：US13068192

申请日：2011-05-04

Applicant: Yan Wang ,  Timothy V. Kalthoff ,  Michael A. Wu

Inventor： Yan Wang ,  Timothy V. Kalthoff ,  Michael A. Wu

IPC: H03M1/12

CPC classification number: H03M1/1295 ,  H03M1/468

Abstract: A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN−) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.

Abstract translation: 开关电容器电路（10,32或32A）通过将加法导体（13）的顶板切换到第一参考电压（VSS）而将第一信号（VIN +）采样到第一电容器（C1或CIN1）上，并且 将其底板切换到第一信号。 将第二信号（VIN-）通过将其顶板切换到第二信号并将其底板切换到第一参考电压而被采样到第二电容器（C3或CIN3）上。 在采样之后，第二电容器的顶板耦合到第一电容器的顶板。 第二电容器的底板耦合到第一参考电压。 第一电容器的底板耦合到第二参考电压（VDD或VREF），从而从第一导体（13）消除共模输入电压分量的至少一部分，将采样的差分电荷保持在求和 并在其上建立预定的共模电压，并且防止求和导体具有允许从其中泄漏电荷的电压。 开关电容电路可以是SAR，积分器或放大器。