公开(公告)号：US20070028128A1

公开(公告)日：2007-02-01

申请号：US11192499

申请日：2005-07-29

申请人： Te-Lin Ping

发明人： Te-Lin Ping

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3265 ,  Y02D10/153 ,  Y02D50/20

摘要： A power-saving method of continuous display and effective cost in a system that includes memory directly accessed by a CPU and at least one display device within vertical blanking. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the d display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process.

摘要翻译： 在包括由CPU直接访问的存储器和在垂直消隐中的至少一个显示设备的系统中的连续显示和有效成本的省电方法。 该方法包括以下步骤：发出省电相关消息; 省掉与节能相关的消息，其中没有设置省电相关标志; 设置省电相关标志; 设置CPU中的VID / FID待定位，其中发生d显示/显示的垂直消隐，并清除省电相关标志，其中设置了省电相关标志，并执行省电处理。

公开(公告)号：US20110296134A1

公开(公告)日：2011-12-01

申请号：US13116751

申请日：2011-05-26

申请人： Te-Lin PING ,  Han-Chiang Su

发明人： Te-Lin PING ,  Han-Chiang Su

IPC分类号： G06F12/10

CPC分类号： G06F12/02

摘要： An adaptive memory address translation method includes the following steps. Multiple request instructions are received. A memory address corresponding to each request instruction includes a bank address. The memory addresses corresponding to the request instructions are translated, such that the bank addresses corresponding to at least one part of the any two adjacent request instructions are different. A numerical translation is utilized to translate the memory addresses corresponding to the request instructions, such that the memory addresses corresponding to the any two adjacent request instructions have less different bits.

摘要翻译： 自适应存储器地址转换方法包括以下步骤。 接收到多个请求指令。 对应于每个请求指令的存储器地址包括存储体地址。 与请求指令相对应的存储器地址被转换，使得对应于任何两个相邻请求指令的至少一部分的存储体地址不同。 使用数字转换来转换对应于请求指令的存储器地址，使得对应于任何两个相邻请求指令的存储器地址具有较少不同的位。

公开(公告)号：US20100299488A1

公开(公告)日：2010-11-25

申请号：US12534160

申请日：2009-08-03

申请人： Te-Lin Ping ,  I-Huan Huang

发明人： Te-Lin Ping ,  I-Huan Huang

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F12/10 ,  G06F13/1631

摘要： A dynamic memory access method includes following steps. First, many data access commands are received. Each of the data access commands accesses a dynamic memory according to a page address and a bank address. Next, whether an access data to be accessed by the corresponding data access command is an instantaneous data or a non-instantaneous data is determined. Then, the page and bank addresses of each of the data access commands are respectively compared with a previously page and bank addresses at a previous time used for accessing the dynamic memory, such that an address hit status is obtained. Next, a service sequence is generated according to whether each of the data access commands is an instantaneous or instantaneous data and the address hit status of the commands. Finally, each of the data access commands is executed to access the dynamic memory sequentially according to the service sequence.

摘要翻译： 动态存储器访问方法包括以下步骤。 首先，接收到许多数据访问命令。 每个数据访问命令根据页面地址和银行地址访问动态存储器。 接下来，确定由相应的数据访问命令访问的访问数据是否是瞬时数据或非瞬时数据。 然后，将每个数据访问命令的页面和存储体地址分别与用于访问动态存储器的先前时间的页面和存储体地址进行比较，从而获得地址命中状态。 接下来，根据每个数据访问命令是瞬时数据还是瞬时数据以及命令的地址命中状态来生成服务序列。 最后，执行每个数据访问命令以根据服务顺序顺序地访问动态存储器。

公开(公告)号：US20100180141A1

公开(公告)日：2010-07-15

申请号：US12426926

申请日：2009-04-20

申请人： Te-Lin Ping ,  Yao-Cheng Chuang

发明人： Te-Lin Ping ,  Yao-Cheng Chuang

IPC分类号： G06F1/12

CPC分类号： G06F1/10

摘要： A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a signal delay time according to a delay adjustment value corresponding to the system-environment monitor value index.

摘要翻译： 电路系统定期检查系统环境监视值，然后在环境调整查找表中获取与系统环境监视值对应的系统环境监视值索引。 最后，电路系统根据对应于系统环境监控值的延迟调整值调整信号延迟时间。

公开(公告)号：US07421600B2

公开(公告)日：2008-09-02

申请号：US11192499

申请日：2005-07-29

申请人： Te-Lin Ping

发明人： Te-Lin Ping

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3265 ,  Y02D10/153 ,  Y02D50/20

摘要： A power-saving method of continuous display and effective cost in a system that includes memory directly accessed by a CPU and at least one display device within vertical blanking. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process.

摘要翻译： 在包括由CPU直接访问的存储器和在垂直消隐中的至少一个显示设备的系统中的连续显示和有效成本的节电方法。 该方法包括以下步骤：发出省电相关消息; 省掉与节能相关的消息，其中没有设置省电相关标志; 设置省电相关标志; 设置CPU中的VID / FID待处理位，其中发生显示/显示的垂直消隐，并清除省电相关标志，其中设置了省电相关标志，并执行省电处理。

公开(公告)号：US20070083782A1

公开(公告)日：2007-04-12

申请号：US11163250

申请日：2005-10-11

申请人： TE-LIN PING

发明人： TE-LIN PING

IPC分类号： G06F1/26

CPC分类号： G06F1/3203

摘要： A Power-saving method, which is able to configure not only the CPU but also the other computer devices, such as the host bus, GUI engine, South Bridge control engine . . . etc., into Power-saving state, has been proposed. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the d display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process. The Power-saving related flag may be built-in North Bridge, South Bridge or CPU.

摘要翻译： 一种省电方式，不仅可以配置CPU，还可以配置其他计算机设备，如主机总线，GUI引擎，南桥控制引擎。 。 。 等等，进入省电状态，已经提出。 该方法包括以下步骤：发出省电相关消息; 省掉与节能相关的消息，其中没有设置省电相关标志; 设置省电相关标志; 设置CPU中的VID / FID待定位，其中发生d显示/显示的垂直消隐，并清除省电相关标志，其中设置了省电相关标志，并执行省电处理。 省电相关标志可能内置北桥，南桥或CPU。

公开(公告)号：US20110235722A1

公开(公告)日：2011-09-29

申请号：US13064448

申请日：2011-03-25

申请人： Te-Lin Ping ,  Shi-Yen Huang

发明人： Te-Lin Ping ,  Shi-Yen Huang

IPC分类号： H04N7/26 ,  G06F9/46

CPC分类号： G06F9/544 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44

摘要： A computer system architecture including a first buffer, a second buffer, a sub-system and a CPU is provided. The sub-system carries out a first task to obtain first returned information, stores the first returned information in the first buffer and sets up a first occupancy flag to the first buffer. Next, the sub-system carries out a second task to obtain second returned information, stores the second returned information in the second buffer, and sets up a second occupancy flag to the second buffer. The CPU reads the first returned information and eliminates the first occupancy flag. After the second returned information is stored in the second buffer and the first occupancy flag is eliminated, the sub-system continuously carries out a third task to obtain third returned information, stores the third returned information in the first buffer, and sets up the first occupancy flag to the first buffer.

摘要翻译： 提供了包括第一缓冲器，第二缓冲器，子系统和CPU的计算机系统架构。 子系统执行第一任务以获得第一返回信息，将第一返回信息存储在第一缓冲器中，并将第一占用标志设置到第一缓冲器。 接下来，子系统执行第二任务以获得第二返回信息，将第二返回信息存储在第二缓冲器中，并将第二占用标志设置到第二缓冲器。 CPU读取第一个返回的信息，并消除第一个占用标志。 在将第二返回信息存储在第二缓冲器中并且消除第一占用标志之后，子系统连续地执行第三任务以获得第三返回信息，将第三返回信息存储在第一缓冲器中，并且设置第一 占用标志到第一个缓冲区。

公开(公告)号：US20110219198A1

公开(公告)日：2011-09-08

申请号：US13042013

申请日：2011-03-07

申请人： Te-Lin PING ,  I-Huan Huang

发明人： Te-Lin PING ,  I-Huan Huang

IPC分类号： G06F12/00

CPC分类号： G06F12/00

摘要： A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

摘要翻译： 存储器控制系统包括第一队列单元，第二队列单元，第一变换单元，第二变换单元，仲裁器和控制单元。 第一队列单元临时存储多个第一请求指令。 第二队列单元临时存储多个第二请求指令。 第一变换单元选择性地重新分配对应于这些第一请求指令的存储器地址。 第二变换单元选择性地重新分配对应于这些第二请求指令的存储器地址。 仲裁器将第一请求指令和第二请求指令立即调度到存储器。 控制单元将第一请求指令的带宽与第二请求指令的带宽进行比较，并且根据比较结果控制第一变换单元和第二变换单元进行重新分配操作。

公开(公告)号：US20070067502A1

公开(公告)日：2007-03-22

申请号：US11233590

申请日：2005-09-22

申请人： Te-Lin Ping

发明人： Te-Lin Ping

IPC分类号： G06F3/00

CPC分类号： G06F9/4881

摘要： A method for preventing the long latency event in the working procedure of the processor is disclosed, wherein the method comprises one step of checking whether a status happens or not. When the status happens, the processor would release the resource for specific time duration to process other works in order to prevent the long latency event.

摘要翻译： 公开了一种用于防止处理器的工作过程中长时间延迟事件的方法，其中该方法包括检查状态是否发生的一个步骤。 当状态发生时，处理器将释放特定持续时间的资源以处理其他工作，以防止长延迟事件。

公开(公告)号：US06667926B1

公开(公告)日：2003-12-23

申请号：US10236955

申请日：2002-09-09

申请人： Yi-Hung Chen ,  Ming-Hsien Lee ,  Chia-Hsien Chou ,  Tsan-Hwi Chen ,  Te-Lin Ping

发明人： Yi-Hung Chen ,  Ming-Hsien Lee ,  Chia-Hsien Chou ,  Tsan-Hwi Chen ,  Te-Lin Ping

IPC分类号： G11C700

CPC分类号： G11C7/22 ,  G06F13/161

摘要： A memory read/write arbitration method is disclosed. The memory read/write arbitration method, which is utilized in a memory controller for increasing row hit rate and decreasing the delay of memory access, comprises: providing a arbitrator; providing a read request fifo queue having command read requests; providing a write request fifo queue having command write requests; performing a judgment step for generating a priority, wherein the judgment step comprises: performing a first sub-judgment step to determine that a command read request of the command read requests has priority over a command write request of the command write requests, or the command write request can be forwarded to a second sub-judgment step under adaptive first-step conditions; performing the second sub-judgment step to determine the read request has priority over the command write request from the first sub-judgment step, or the command write request from the first sub-judgment has priority over the command read request. Therefore, by the memory read/write arbitration method of the present invention, the row hit rate and the bandwidth utilization of memory module are increased through the applied judgment step.

摘要翻译： 公开了一种存储器读/写仲裁方法。 存储器读/写仲裁方法，其用于存储器控制器中以增加行命中率并减少存储器访问的延迟，包括：提供仲裁器; 提供具有命令读请求的读请求fifo队列; 提供具有命令写请求的写请求fifo队列; 执行用于生成优先级的判断步骤，其中所述判断步骤包括：执行第一子判断步骤以确定所述命令读请求的命令读请求优先于所述命令写请求的命令写请求，或所述命令 写入请求可以在自适应的第一步条件下被转发到第二子判断步骤; 执行第二子判断步骤以确定读取请求具有来自第一子判断步骤的命令写入请求的优先级，或者来自第一副判断的命令写入请求优先于命令读取请求。 因此，通过本发明的存储器读/写仲裁方法，通过应用判断步骤增加存储器模块的行命中率和带宽利用率。