公开(公告)号：US5316974A

公开(公告)日：1994-05-31

申请号：US516637

申请日：1990-04-30

Applicant: Sue E. Crank

Inventor： Sue E. Crank

IPC: H01L21/48 ,  H01L21/768 ,  H01L21/00 ,  H01L21/02 ,  H01L21/44

CPC classification number: H01L21/4846 ,  H01L21/76838 ,  Y10S438/963

Abstract: An improved metallized structure (10) is formed from a copper seed layer (46) and a copper structure (48). Semiconductor devices to be connected (16-18) are covered by a conductive barrier layer (20). An oxide layer (28) is then deposited over the barrier layer (20) and patterned using standard photolithographic techniques and an anisotropic plasma etch. Vertical sidewalls (36-38) are formed by the etch and an HF deglaze. A seed layer (44-46) is then sputtered onto a photoresist layer (30) and the exposed barrier layer (20). After stripping the photoresist (30) and the seed layer (44) thereon, the copper structure (48) is electroplated over the remaining seed layer (46). The structure (48) thus formed has approximately vertical sidewalls (24-26) for improved contact with subsequent layers.

Abstract translation: 改进的金属化结构（10）由铜籽晶层（46）和铜结构（48）形成。 要连接的半导体器件（16-18）被导电阻挡层（20）覆盖。 然后将氧化物层（28）沉积在阻挡层（20）上，并使用标准光刻技术和各向异性等离子体蚀刻进行图案化。 垂直侧壁（36-38）通过蚀刻和HF去潮形成。 然后将种子层（44-46）溅射到光致抗蚀剂层（30）和暴露的阻挡层（20）上。 在剥离光致抗蚀剂（30）和种子层（44）之后，将铜结构（48）电镀在剩余的种子层（46）上。 由此形成的结构（48）具有大致垂直的侧壁（24-26），用于改进与后续层的接触。

公开(公告)号：US4874723A

公开(公告)日：1989-10-17

申请号：US74375

申请日：1987-07-16

Applicant: Rhett B. Jucha ,  Duane E. Carter ,  Cecil J. Davis ,  Sue E. Crank

Inventor： Rhett B. Jucha ,  Duane E. Carter ,  Cecil J. Davis ,  Sue E. Crank

IPC: H01L21/3213

CPC classification number: H01L21/32136 ,  Y10S148/051 ,  Y10S438/963

Abstract: A thin film etching process, wherein the rate of deposition of a robust sidewall passivant is controlled so that passivants can be continually deposited on the sidewalls of the resist pattern to change the geometry of the resist pattern during the processing step. That is, the existing pattern is modified as if a sidewall filament has been deposited on it, which can be advantageous for many purposes, without the added process complexity required by a sidewall filament process.

Abstract translation: 薄膜蚀刻工艺，其中控制坚固的侧壁钝化剂的沉积速率，使得钝化剂可以连续沉积在抗蚀剂图案的侧壁上，以在加工步骤期间改变抗蚀剂图案的几何形状。 也就是说，现有的图案被修改，好像侧壁细丝已经沉积在其上，这对于许多目的而言是有利的，而不需要由侧壁细丝工艺所需的附加工艺复杂性。

公开(公告)号：US4863558A

公开(公告)日：1989-09-05

申请号：US188178

申请日：1988-04-27

Applicant: Rhett B. Jucha ,  Cecil J. Davis ,  Sue E. Crank

Inventor： Rhett B. Jucha ,  Cecil J. Davis ,  Sue E. Crank

IPC: C23C14/56 ,  C23F4/00 ,  H01L21/00 ,  H01L21/677

CPC classification number: H01L21/67748 ,  C23C14/56 ,  C23F4/00 ,  H01L21/67115 ,  H01L21/67751

Abstract: Tungsten is rapidly and anisotropically etched under plasma bombardment conditions by using a feed gas mixture which includes a fluorine source (such as SF.sub.6) plus a bromine source (such as HBr), plus a hydrocarbon source (e.g., an alkyl, such as methane).

Abstract translation: 通过使用包括氟源（例如SF 6）加溴源（例如HBr），加上烃源（例如烷基，例如甲烷）的进料气体混合物，在等离子体轰击条件下快速和各向异性地蚀刻钨， 。

公开(公告)号：US4849067A

公开(公告)日：1989-07-18

申请号：US74411

申请日：1987-07-16

Applicant: Rhett B. Jucha ,  Cecil J. Davis ,  Duane E. Carter ,  Sue E. Crank ,  John I. Jones

Inventor： Rhett B. Jucha ,  Cecil J. Davis ,  Duane E. Carter ,  Sue E. Crank ,  John I. Jones

IPC: C23F4/00 ,  H01L21/3213

CPC classification number: C23F4/00 ,  H01L21/32136

Abstract: A fluorine based metal etch chemistry, wherein an admixture of etch products (or species which are closely related to etch products) is added during the post etch stage, i.e. during the stage when the pattern has partially cleared by overetch is not yet completed, to maintain the balance of chemistries which provides selectivity and anisotropy. In a tungsten etch, WF.sub.6 is usefully added during the post etch period to provide this loading.

Abstract translation: 一种氟基金属蚀刻化学，其中在后蚀刻阶段，即在通过过蚀刻部分清除图案尚未完成的阶段期间添加蚀刻产物（或与蚀刻产物密切相关的物质）的混合物，至 维持提供选择性和各向异性的化学物质的平衡。 在钨蚀刻中，在后蚀刻期间有用地加入WF6以提供该负载。

公开(公告)号：US07355255B2

公开(公告)日：2008-04-08

申请号：US11678950

申请日：2007-02-26

Applicant: Peijun J. Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue E. Crank ,  Thomas D. Bonifield ,  Homi C. Mogul

Inventor： Peijun J. Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue E. Crank ,  Thomas D. Bonifield ,  Homi C. Mogul

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/28518 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

Abstract translation: 本发明提供一种半导体装置及其制造方法以及包括该半导体装置的集成电路的制造方法。 除了其它元件之外，半导体器件可以包括衬底（110）以及位于衬底（110）上方的硅化镍区域（170），所述硅化镍区域（170）具有位于其中的铟的量。

公开(公告)号：US07029967B2

公开(公告)日：2006-04-18

申请号：US10896599

申请日：2004-07-21

Applicant: Song Zhao ,  Sue E. Crank ,  Amitava Chatterjee ,  Kaiping Liu ,  Jiong-Ping Lu ,  Donald S. Miles ,  Duofeng Yue ,  Lance S. Robertson

Inventor： Song Zhao ,  Sue E. Crank ,  Amitava Chatterjee ,  Kaiping Liu ,  Jiong-Ping Lu ,  Donald S. Miles ,  Duofeng Yue ,  Lance S. Robertson

IPC: H01L21/8238 ,  H01L21/331

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665

Abstract: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.

Abstract translation: 描述了在源区和漏区（160,170）中形成金属硅化物区域的方法。 在源极和漏极区域（160,170）的热退火之前，将锗注入到与栅极结构（60,70）相邻形成的侧壁结构（90,95）附近的半导体衬底中。 植入的锗物质在半导体衬底中的位置将与源区和漏区（160,170）重叠。 在源极和漏极区域（160,170）的热退火之后，注入的锗防止形成金属硅化物尖峰。