公开(公告)号：US20110141696A1

公开(公告)日：2011-06-16

申请号：US12966728

申请日：2010-12-13

申请人： Stephen J. Gaul ,  Steven Howard Voldman ,  Jean-Michel Tschann

发明人： Stephen J. Gaul ,  Steven Howard Voldman ,  Jean-Michel Tschann

IPC分类号： H05K7/20 ,  H01L21/50

CPC分类号： H01L29/861 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3732 ,  H01L23/60 ,  H01L29/0653 ,  H01L29/73 ,  H01L29/737 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： Embodiments described herein provide a chip, comprising a first device on a substrate and a second device on the substrate. The chip further comprises a heat distribution structure in thermal proximity to the first device and the second device, wherein the heat distribution structure is thermally isolated and reduces a thermal gradient between the first device and the second device.

摘要翻译： 本文描述的实施例提供一种芯片，其包括在基板上的第一器件和衬底上的第二器件。 芯片还包括热接近第一器件和第二器件的热分布结构，其中热分布结构被热隔离并且减小第一器件和第二器件之间的热梯度。

公开(公告)号：US20100323487A1

公开(公告)日：2010-12-23

申请号：US12868428

申请日：2010-08-25

申请人： Stephen J. Gaul ,  Michael D. Church ,  Brent R. Doyle

发明人： Stephen J. Gaul ,  Michael D. Church ,  Brent R. Doyle

IPC分类号： H01L21/762

CPC分类号： H01L27/088 ,  H01L21/761 ,  H01L21/823481 ,  H01L29/1083

摘要： A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

摘要翻译： “标签”MOS器件提供辐射硬度，同时支持减小栅极宽度要求。 “标签式”MOS器件还采用了机身连接环，可减少磁场阈值泄漏。 在一个实现中，“标签式”MOS器件被设计成使得突片的宽度基于MOS器件的至少沟道长度，使得器件的源极和漏极区域之间的辐射诱导寄生传导路径具有 电阻高于器件沟道电阻。

公开(公告)号：US5561303A

公开(公告)日：1996-10-01

申请号：US248844

申请日：1994-05-25

申请人： Gregory A. Schrantz ,  Stephen J. Gaul

发明人： Gregory A. Schrantz ,  Stephen J. Gaul

IPC分类号： H01L23/373 ,  H01L31/0312 ,  H01L29/04 ,  H01L31/036

CPC分类号： H01L23/3732 ,  H01L2924/0002

摘要： An integrated circuit structure containing dielectrically isolated islands having heat dissipation paths of enhanced thermal conductivity. A semiconductor structure comprises a first layer of crystalline material with a layer comprising polycrystalline diamond formed over the first layer. A layer of polycrystalline silicon is formed over the diamond containing layer and a layer of monocrystalline material is formed over the polycrystalline silicon.

摘要翻译： 包含具有增强导热性的散热路径的介电隔离岛的集成电路结构。 半导体结构包括第一层结晶材料，其中包含在第一层上形成的多晶金刚石层。 在含金刚石层上形成多晶硅层，并在多晶硅上形成一层单晶材料。

公开(公告)号：US5240876A

公开(公告)日：1993-08-31

申请号：US891910

申请日：1992-06-01

申请人： Stephen J. Gaul ,  George V. Rouse

发明人： Stephen J. Gaul ,  George V. Rouse

IPC分类号： H01L21/20 ,  H01L21/322 ,  H01L21/762 ,  H01L29/786

CPC分类号： H01L21/3226 ,  H01L21/2007 ,  H01L21/76251 ,  H01L29/78603 ,  Y10S438/904

摘要： An SOI wafer is formed having a silicon-germanium layer between the epitaxial layer of the device and the insulative layer. The process includes bonding a second substrate to a silicon-germanium layer on a first substrate by an intermediate insulative layer. The first substrate is removed down to the silicon-germanium layer and the silicon layer is epitaxially formed on the silicon-germanium layer.

摘要翻译： 形成在器件的外延层和绝缘层之间具有硅 - 锗层的SOI晶片。 该方法包括通过中间绝缘层将第二衬底接合在第一衬底上的硅 - 锗层上。 将第一衬底除去到硅 - 锗层，并且在硅 - 锗层上外延形成硅层。

公开(公告)号：US5037765A

公开(公告)日：1991-08-06

申请号：US465314

申请日：1990-01-12

申请人： Stephen J. Gaul ,  Craig J. McLachlan

发明人： Stephen J. Gaul ,  Craig J. McLachlan

IPC分类号： G01L9/00 ,  G02B6/42

CPC分类号： G02B6/4214 ,  G01L9/0042 ,  G02B6/42

摘要： Integrated circuits are formed by bonding two substrates together on a moat or recess. If the moat is exposed at a side wall, an optical fiber is inserted therein and communicates optically with a photoelectric device in the substrate by a slant side wall of the moat. If the moat is sealed by a cover layer resulting from removing all or most of the top substrate leaving the bonding layer as a cover, a pressure responsive device is formed on the cover layer directly or in the remaining top substrate over the sealed cavity.

摘要翻译： 集成电路通过将两个衬底粘合在护城河或凹槽上而形成。 如果护城河暴露在侧壁处，则将光纤插入其中并通过护城河的倾斜侧壁与基板中的光电装置进行光学连接。 如果通过将离开结合层的所有或大部分顶部基底作为盖而被覆盖层密封，则在覆盖层上直接或在剩余的顶部基底上形成压力响应装置，在密封空腔上。

公开(公告)号：US08859337B2

公开(公告)日：2014-10-14

申请号：US12966728

申请日：2010-12-13

申请人： Stephen J Gaul ,  Steven Howard Voldman ,  Jean-Michel Tschann

发明人： Stephen J Gaul ,  Steven Howard Voldman ,  Jean-Michel Tschann

IPC分类号： H01L21/00 ,  H01L29/861 ,  H01L23/367 ,  H01L23/60 ,  H01L23/373 ,  H01L29/737 ,  H01L29/73 ,  H01L29/06

CPC分类号： H01L29/861 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3732 ,  H01L23/60 ,  H01L29/0653 ,  H01L29/73 ,  H01L29/737 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： Embodiments described herein provide a chip, comprising a first device on a substrate and a second device on the substrate. The chip further comprises a heat distribution structure in thermal proximity to the first device and the second device, wherein the heat distribution structure is thermally isolated and reduces a thermal gradient between the first device and the second device.

摘要翻译： 本文描述的实施例提供一种芯片，其包括在基板上的第一器件和衬底上的第二器件。 芯片还包括热接近第一器件和第二器件的热分布结构，其中热分布结构被热隔离并且减小第一器件和第二器件之间的热梯度。

公开(公告)号：US20120256193A1

公开(公告)日：2012-10-11

申请号：US13165396

申请日：2011-06-21

申请人： Francois Hebert ,  Stephen J. Gaul ,  Shea Petricek

发明人： Francois Hebert ,  Stephen J. Gaul ,  Shea Petricek

IPC分类号： H01L29/02 ,  H01L29/06 ,  H01L21/02 ,  H01L29/92

CPC分类号： H01L23/5223 ,  H01L21/823418 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0629 ,  H01L27/088 ,  H01L28/60 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor structure such as a power converter with an integrated capacitor is provided, and comprises a semiconductor substrate, a high-side output power device over the substrate at a first location, and a low-side output power device over the substrate at a second location adjacent to the first location. A first metal layer is over the high-side output power device and electrically coupled to the high-side output power device, and a second metal layer is over the low-side output power device and electrically coupled to the low-side output power device. A dielectric layer is over a portion of the first metal layer and a portion of the second metal layer, and a top metal layer is over the dielectric layer. The integrated capacitor comprises a first bottom electrode that includes the portion of the first metal layer, a second bottom electrode that includes the portion of the second metal layer, the dielectric layer over the portions of the first and second metal layers, and a top electrode that includes the top metal layer over the dielectric layer.

摘要翻译： 提供了诸如具有集成电容器的功率转换器的半导体结构，并且包括半导体衬底，在第一位置处的衬底上的高侧输出功率器件和在第二位置处的衬底上的低侧输出功率器件 位置与第一个位置相邻。 第一金属层位于高侧输出功率器件的上方并且电耦合到高侧输出功率器件，并且第二金属层在低侧输出功率器件的上方并且电耦合到低侧输出功率器件 。 电介质层位于第一金属层的一部分和第二金属层的一部分上，并且顶部金属层在电介质层的上方。 集成电容器包括包括第一金属层的部分的第一底部电极，包括第二金属层的部分的第二底部电极，第一和第二金属层的部分上的电介质层，以及顶部电极 其包括在电介质层上的顶部金属层。

公开(公告)号：US5448102A

公开(公告)日：1995-09-05

申请号：US292588

申请日：1994-08-18

申请人： Stephen J. Gaul ,  Donald F. Hemmenway

发明人： Stephen J. Gaul ,  Donald F. Hemmenway

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/76

CPC分类号： H01L21/762 ,  H01L21/76232 ,  H01L21/763

摘要： In a microelectronic device formed on a substrate 12, a pair of trenches 30, 36 branch at their intersection to provide branches 31-34 surrounding a sacrificial island 42. Sacrificial island 42 may comprise substrate material or other material or a void for absorbing the axial stresses propagated along the lengths of trenches 30, 36.

摘要翻译： 在形成在衬底12上的微电子器件中，一对沟槽30,36在其相交处分支，以提供围绕牺牲岛42的分支31-34。牺牲岛42可包括衬底材料或其它材料或用于吸收轴向 应力沿沟槽30,36的长度传播。

公开(公告)号：US4968628A

公开(公告)日：1990-11-06

申请号：US282064

申请日：1988-12-09

申请人： Jose A. Delgado ,  Stephen J. Gaul ,  Craig J. McLachlan ,  George V. Rouse

发明人： Jose A. Delgado ,  Stephen J. Gaul ,  Craig J. McLachlan ,  George V. Rouse

IPC分类号： H01L21/762

CPC分类号： H01L21/76251 ,  Y10S148/012 ,  Y10S438/928

摘要： A method including forming an alignment moat of a first depth on a first surface of a substrate and performing all backside processing, forming a first oxide layer on the first surface and oxide bonding it to a handling wafer by oxide bonding. The substrate is then thinned from a second surface opposite the first surface down to a thickness less than the depth of the alignment moat so the alignment moat is exposed at a third surface for front side processing.

摘要翻译： 一种方法，包括在衬底的第一表面上形成第一深度的对准护套并执行所有背面处理，在所述第一表面上形成第一氧化物层，并通过氧化物结合将其氧化成处理晶片。 然后将衬底从与第一表面相对的第二表面减薄到小于对准护环的深度的厚度，使得对准护套在第三表面处暴露以进行正面处理。

公开(公告)号：US06211056B1

公开(公告)日：2001-04-03

申请号：US09199292

申请日：1998-11-24

申请人： Patrick A. Begley ,  William R. Young ,  Anthony L. Rivoli ,  Jose Avelino Delgado ,  Stephen J. Gaul

发明人： Patrick A. Begley ,  William R. Young ,  Anthony L. Rivoli ,  Jose Avelino Delgado ,  Stephen J. Gaul

IPC分类号： H01L214763

CPC分类号： H01L28/10 ,  H01L21/7682 ,  H01L23/5221 ,  H01L2924/0002 ,  H01L2924/00

摘要： Conductive elements which provide interconnections (air bridges between circuits) and components such as capacitors and inductors may be incorporated in the devices in a manner to reduce parasitic effects in the operation of the devices while providing close spacing which enhances the performance of the devices at high frequency. Separate substrates are provided respectively having the integrated circuits formed therein and covering, preferably sealing the integrated circuits. The air bridge conductive components (interconnections, capacitors or inductors) are formed separately in the covering substrate which is assembled with the substrate having the integrated circuit as a lid which seals and packages the circuits and the conductive element or component contained in the lid. The conductive component may be separated by cavities formed in the lid substrate or in the substrate having the integrated circuit device already formed therein. Assembly may take place at temperatures lower than necessary for fusion bonding and diffusion commonly used in the fabrication of integrated circuits. Bonds which are used may be metal, oxide or plastic (polymer) bonding material.

摘要翻译： 提供互连（电路之间的空气桥）和诸如电容器和电感器的部件的导电元件可以以减少器件操作中的寄生效应的方式并入器件中，同时提供紧密的间隔，这增强了器件在高处的性能 频率。 分别提供分离的基板，其中形成有集成电路并覆盖，优选地密封集成电路。 空气桥导电部件（互连，电容器或电感器）分别形成在与具有集成电路的基板组装的覆盖基板上，该基板具有密封并封装电路和包含在盖中的导电元件或部件的盖。 导电部件可以由形成在盖基板中的空腔或已经形成有集成电路器件的基板分离。 组装可能发生在集成电路制造中常用的熔接和扩散所需的温度以下。 使用的债​​券可以是金属，氧化物或塑料（聚合物）结合材料。