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    Mapping between program states and data patterns
    3.
    发明授权
    Mapping between program states and data patterns 有权
    程序状态和数据模式之间的映射

    公开(公告)号：US08788743B2

    公开(公告)日：2014-07-22

    申请号：US13444314

    申请日：2012-04-11

    申请人： Sivagnanam Parthasarathy ,  Patrick R. Khayat ,  Mustafa N. Kaynak ,  Zhenlei Shen

    发明人： Sivagnanam Parthasarathy ,  Patrick R. Khayat ,  Mustafa N. Kaynak ,  Zhenlei Shen

    IPC分类号： G06F12/00 ,  G11C16/00 ,  G06F12/06 ,  G11C11/56 ,  G11C16/10

    CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F12/06 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C13/0002 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  H03M7/14

    摘要： The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G.

    摘要翻译： 本公开包括用于在程序状态和数据模式之间进行映射的方法和装置。 一种方法包括：对一组G存储器单元进行编程，使得该组的各个程序状态的组合映射到与接收到的N单位数据模式对应的星座点，该组用于存储每个存储单元的N / G个数据单元 ; 其中所述星座点是与将所述存储器单元组的各个程序状态组合映射到N个单位数据模式相关联的星座的多个星座点中的一个; 并且其中所述星座包括第一映射外壳和第二映射外壳，所述星座点对应于相应的第一和第二映射外壳，至少部分地基于等于G的等级的多项式表达式确定。

    Methods to improve ACS performance
    5.
    发明授权
    Methods to improve ACS performance 有权
    提高ACS性能的方法

    公开(公告)号：US09021342B2

    公开(公告)日：2015-04-28

    申请号：US12924658

    申请日：2010-10-01

    申请人： Sivagnanam Parthasarathy ,  Lun Bin Huang

    发明人： Sivagnanam Parthasarathy ,  Lun Bin Huang

    IPC分类号： H03M13/03 ,  H03M13/41

    CPC分类号： H03M13/4146 ,  H03M13/4107

    摘要： In one embodiment, systems and methods of operating a SOVA system is disclosed that comprises determining the start and stop values for a trellis tree and using the start and stop values to determine the initial states of a plurality of branches within the trellis tree.

    摘要翻译： 在一个实施例中，公开了一种操作SOVA系统的系统和方法，其包括确定网格树的开始和停止值，并使用开始和停止值来确定网格树内的多个分支的初始状态。

    Closely coupled vector sequencers for a read channel pipeline
    6.
    发明授权
    Closely coupled vector sequencers for a read channel pipeline 有权
    用于读通道管道的紧耦合矢量定序器

    公开(公告)号：US08379339B2

    公开(公告)日：2013-02-19

    申请号：US12896609

    申请日：2010-10-01

    申请人： Sivagnanam Parthasarathy ,  Alessandro Risso ,  Dillip Dash

    发明人： Sivagnanam Parthasarathy ,  Alessandro Risso ,  Dillip Dash

    IPC分类号： G11B5/09

    CPC分类号： G11B5/09 ,  G11B20/10009 ,  G11B20/10027 ,  G11B20/10296 ,  G11B2220/2516

    摘要： A system and method involving a read channel pipeline having a plurality of vector sequencers that may be used to control the processing blocks. In one embodiment, a read channel pipeline may include processing blocks that may be controlled a command word provided by vector sequencers. Incoming data may be delineated by identifying an early period, a steady-state period, and a trailing period. Instead of controlling these blocks with a static state machine controller, a plurality of vector sequencers are coupled to the plurality of processing blocks. Thus, a first vector sequencer may control the processing blocks during the early period and the steady state period, but then hand off control to a second vector sequencer for the trailing period. Using vector sequencers for implementing command words allows for greater programming flexibility once the device has been manufactured and deployed for use.

    摘要翻译： 一种涉及具有可用于控制处理块的多个向量定序器的读通道流水线的系统和方法。 在一个实施例中，读通道流水线可以包括可以被控制由矢量定序器提供的命令字的处理块。 可以通过识别早期，稳定状态时段和尾随时段来描绘输入数据。 代替使用静态机器控制器控制这些块，多个向量定序器被耦合到多个处理块。 因此，第一矢量定序器可以在早期和稳定状态时段期间控制处理块，但是在后续周期中切换到第二矢量定序器的控制。 使用矢量顺控程序来实现命令字可以在设备制造和部署使用后实现更大的编程灵活性。

    Channel constrained code aware interleaver
    7.
    发明授权
    Channel constrained code aware interleaver 有权
    频道约束码识别交织器

    公开(公告)号：US08055973B2

    公开(公告)日：2011-11-08

    申请号：US12479652

    申请日：2009-06-05

    申请人： Shayan Srinivasa Garani ,  Nicholas J. Richardson ,  Xinde Hu ,  Sivagnanam Parthasarathy

    发明人： Shayan Srinivasa Garani ,  Nicholas J. Richardson ,  Xinde Hu ,  Sivagnanam Parthasarathy

    IPC分类号： H03M13/00

    CPC分类号： H03M13/27 ,  G11B2020/10796 ,  G11B2020/185

    摘要： An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.

    摘要翻译： 基于施加在信道和代码域中的联合约束来构造交织器。 通过考虑ISI存储器深度和奇偶校验矩阵内节点的连通性，使用顺序优化算法将码元间干扰（ISI）域中的比特映射到码域。 考虑了主要设计约束，例如并行因素，使得所提出的系统在满足高吞吐量要求方面符合硬件要求。

    Max-log-map equivalence log likelihood ratio generation soft Viterbi architecture system and method
    8.
    发明申请
    Max-log-map equivalence log likelihood ratio generation soft Viterbi architecture system and method 有权
    最大对数映射等价对数似然比生成软维特比架构系统和方法

    公开(公告)号：US20110197112A1

    公开(公告)日：2011-08-11

    申请号：US12924707

    申请日：2010-10-01

    申请人： Sivagnanam Parthasarathy ,  Lun Bin Huang ,  Alessandro Risso

    发明人： Sivagnanam Parthasarathy ,  Lun Bin Huang ,  Alessandro Risso

    IPC分类号： H03M13/23 ,  G06F11/10

    CPC分类号： H03M13/4146 ,  G06F11/1076 ,  G11B20/18 ,  H03M13/3905 ,  H03M13/3927 ,  H03M13/4184 ,  H03M13/42 ,  H03M13/6343 ,  H03M13/6502 ,  H04L1/0054 ,  H04L1/0055

    摘要： A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

    摘要翻译： 修改的软输出维特比算法（SOVA）检测器接收软信息值序列，并为每个软信息值确定最佳路径和备用路径，并且进一步确定当给定软件的最佳和替代路径导致相同值时 信息值，是否存在离开替代路径的第三路径，其导致相对于给定软信息值的最佳路径的相反决定。 然后，SOVA检测器在更新最佳路径的可靠性时考虑第三条路径。 改进的SOVA检测器通过Fossorier方法有效地实现了最大对数映射的等效性，并且包括SOVA检测器的前N个级的修正的可靠性度量单位，其中N是给定路径的存储器深度，并且包括用于 检测器的剩余阶段。

    System and method for managing vertical dependencies in a digital signal processor
    10.
    发明授权
    System and method for managing vertical dependencies in a digital signal processor 有权
    用于管理数字信号处理器中的垂直依赖性的系统和方法

    公开(公告)号：US06754807B1

    公开(公告)日：2004-06-22

    申请号：US09652450

    申请日：2000-08-31

    申请人： Sivagnanam Parthasarathy ,  Alexander Driker

    发明人： Sivagnanam Parthasarathy ,  Alexander Driker

    IPC分类号： G06F934

    CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    摘要： An apparatus for managing vertical dependencies between instructions in first and second instruction pipelines includes: 1) identifier (ID) reclaim circuitry for determining a sequential set of retired identifiers associated with retired instructions and for determining a next retire ID sequentially following the set; 2) first ID generation circuitry for sequentially assigning identifiers to destination registers associated with instructions entering the pipelines; 3) second ID generation circuitry associated with the first pipeline for identifying a first dependent source register associated with a first dependent source operand of a first instruction entering the first pipeline and assigning an ID of the first register to the first operand; and 4) instruction scheduling circuitry for comparing the first operand ID of the first instruction with the next retire ID and scheduling the first instruction for execution if the first operand ID is less than or equal to the next retire ID.

    摘要翻译： 一种用于管理第一和第二指令流水线中的指令之间的垂直依赖性的装置，包括：1）标识符（ID）回收电路，用于确定与退休指令相关联的退休标识符的顺序集合，并用于依次确定该组之后的下一个退出ID; 2）用于将标识符顺序地分配给与进入管线的指令相关联的目的地寄存器的第一ID生成电路; 3）与第一流水线相关联的第二ID生成电路，用于识别与第一指令进入第一流水线的第一依赖源操作数相关联的第一依赖源寄存器，并将第一寄存器的ID分配给第一操作数; 以及4）指令调度电路，用于将第一指令的第一操作数ID与下一个退出ID进行比较，并且如果第一操作数ID小于或等于下一个退出ID，则调度第一指令执行。