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    Channel constrained code aware interleaver
    1.
    发明授权
    Channel constrained code aware interleaver 有权
    频道约束码识别交织器

    公开(公告)号：US08055973B2

    公开(公告)日：2011-11-08

    申请号：US12479652

    申请日：2009-06-05

    申请人： Shayan Srinivasa Garani ,  Nicholas J. Richardson ,  Xinde Hu ,  Sivagnanam Parthasarathy

    发明人： Shayan Srinivasa Garani ,  Nicholas J. Richardson ,  Xinde Hu ,  Sivagnanam Parthasarathy

    IPC分类号： H03M13/00

    CPC分类号： H03M13/27 ,  G11B2020/10796 ,  G11B2020/185

    摘要： An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.

    摘要翻译： 基于施加在信道和代码域中的联合约束来构造交织器。 通过考虑ISI存储器深度和奇偶校验矩阵内节点的连通性，使用顺序优化算法将码元间干扰（ISI）域中的比特映射到码域。 考虑了主要设计约束，例如并行因素，使得所提出的系统在满足高吞吐量要求方面符合硬件要求。

    Encoding apparatus, system, and method using low density parity check (LDPC) codes
    3.
    发明授权
    Encoding apparatus, system, and method using low density parity check (LDPC) codes 有权
    使用低密度奇偶校验（LDPC）码的编码装置，系统和方法

    公开(公告)号：US08397125B2

    公开(公告)日：2013-03-12

    申请号：US12587163

    申请日：2009-10-02

    申请人： Shayan Srinivasa Garani

    发明人： Shayan Srinivasa Garani

    IPC分类号： H03M13/00 ,  G06F11/00

    CPC分类号： H03M13/116 ,  H03M13/1142 ,  H03M13/118

    摘要： A system and method is capable of performing a Low Density Parity Check (LDPC) coding operation on-the-fly without using a generator matrix. The system and method includes an input configured to receive data and an output configured to output a plurality of codewords. The system and method also includes a processor coupled between the input and the output. The processor is configured to encode the received data and produce the plurality of codewords using a plurality of parity bits. The processor creates the plurality of parity bits on-the-fly using a portion of an LDPC matrix and a protograph matrix.

    摘要翻译： 一种系统和方法能够在不使用发生器矩阵的情况下即时执行低密度奇偶校验（LDPC）编码操作。 该系统和方法包括被配置为接收数据的输入和被配置为输出多个码字的输出。 该系统和方法还包括耦合在输入和输出之间的处理器。 处理器被配置为对接收的数据进行编码，并使用多个奇偶校验位产生多个码字。 处理器使用LDPC矩阵和原型图矩阵的一部分即时地创建多个奇偶校验位。

    Interlaced iterative system design for 1K-byte block with 512-byte LDPC codewords
    4.
    发明授权
    Interlaced iterative system design for 1K-byte block with 512-byte LDPC codewords 有权
    具有512字节LDPC码字的1K字节块的隔行迭代系统设计

    公开(公告)号：US08255768B2

    公开(公告)日：2012-08-28

    申请号：US12610094

    申请日：2009-10-30

    申请人： Xinde Hu ,  Sivagnanam Parthasarathy ,  Shayan Srinivasa Garani ,  Anthony Weathers ,  Richard Barndt

    发明人： Xinde Hu ,  Sivagnanam Parthasarathy ,  Shayan Srinivasa Garani ,  Anthony Weathers ,  Richard Barndt

    IPC分类号： G06F11/00

    CPC分类号： H03M13/1105 ,  G11B20/1833 ,  G11B2020/185 ,  G11B2220/2516 ,  H03M13/2707 ,  H03M13/2732 ,  H03M13/2957 ,  H03M13/3746 ,  H03M13/4146 ,  H03M13/6331 ,  H03M13/6516

    摘要： To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.

    摘要翻译： 为了允许单个LDPC解码器在具有可比较纠错性能的512B块和4KB块上操作，512KB块被隔行扫描以形成1KB数据序列，并且四个连续的1KB数据序列被级联以形成4KB 部门。 检测器和解码器之间的去隔行器从由检测器输出的单个数据序列形成多个数据序列。 多个数据序列由解交织器和LDPC解码器之间的解交织器，LDPC解码器和LDPD解码器的输出处的交织器分开处理。 隔行扫描器将多个数据序列重组为单个输出。 可以通过在处理期间将相应码字的交织器种子馈送到去交织器和交织器来改进分集。

    CHANNEL CONSTRAINED CODE AWARE INTERLEAVER
    7.
    发明申请
    CHANNEL CONSTRAINED CODE AWARE INTERLEAVER 有权
    频道约束码代理交互

    公开(公告)号：US20100313083A1

    公开(公告)日：2010-12-09

    申请号：US12479652

    申请日：2009-06-05

    申请人： Shayan Srinivasa Garani ,  Nicholas J. Richardson ,  Xinde Hu ,  Sivagnanam Parthasarathy

    发明人： Shayan Srinivasa Garani ,  Nicholas J. Richardson ,  Xinde Hu ,  Sivagnanam Parthasarathy

    IPC分类号： G06F11/00

    CPC分类号： H03M13/27 ,  G11B2020/10796 ,  G11B2020/185

    摘要： An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.

    摘要翻译： 基于施加在信道和代码域中的联合约束来构造交织器。 通过考虑ISI存储器深度和奇偶校验矩阵内节点的连通性，使用顺序优化算法将码元间干扰（ISI）域中的比特映射到码域。 考虑了主要设计约束，例如并行因素，使得所提出的系统在满足高吞吐量要求方面符合硬件要求。