公开(公告)号：US5982315A

公开(公告)日：1999-11-09

申请号：US928874

申请日：1997-09-12

Applicant: Seyfollah S. Bazarjani ,  Saed G. Younis

Inventor： Seyfollah S. Bazarjani ,  Saed G. Younis

IPC: H03M3/02 ,  H03M3/00

CPC classification number: H03M3/418 ,  H03M3/372 ,  H03M3/406 ,  H03M3/47

Abstract: A bandpass .SIGMA..DELTA. DC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, or a two-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a .SIGMA..DELTA. ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 .SIGMA..DELTA. ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass .SIGMA..DELTA. ADC can also be used in conjunction with undersampling to provide a frequency downconversion.

Abstract translation: 利用单回路或MASH架构的带通SIGMA DELTA DC，其中谐振器被实现为延迟单元谐振器，基于延迟单元的谐振器，前向欧拉谐振器或双路交错谐振器。 谐振器可以用诸如有源RC，gm-C，MOSFET-C，开关电容器或开关电流的模拟电路技术来合成。 开关电容器或开关电流电路可以使用单采样，双采样或多采样电路进行设计。 使用开关电容电路的SIGMA DELTA ADC的非严格要求允许ADC以CMOS工艺实现，以最大限度地降低成本并降低功耗。 双采样电路提供了改进的匹配和改进的采样时钟抖动容限。 特别地，带通MASH 4-4 SIGMA DELTA ADC在CDMA应用的过采样比为32时提供85dB的模拟信噪比。 带通SIGMA DELTA ADC也可与欠采样一起使用，以提供频率下变频。

公开(公告)号：US20140093109A1

公开(公告)日：2014-04-03

申请号：US13629855

申请日：2012-09-28

Applicant: Seyfollah S. Bazarjani ,  Arash Mehrabi

Inventor： Seyfollah S. Bazarjani ,  Arash Mehrabi

IPC: H04R5/02

CPC classification number: H04R5/04 ,  H04S1/00 ,  H04S1/005

Abstract: Techniques for removing crosstalk from a system, e.g., an audio system, having first and second (e.g., left and right) channels. In an aspect, first and second output voltages of corresponding first and second amplifiers are sampled during a calibration mode, in which one of the amplifiers is driven with a reference voltage, and the output of the other of the amplifiers is configured to have a high impedance. The sampled first and second output voltages may be digitized for processing by a processor to estimate a crosstalk removal function. The crosstalk removal function may then be multiplied with the input signals and added in a cross-channel manner to the first and second input signals prior to amplification to remove crosstalk from the system. In certain aspects, multiple reference voltages may be applied during the calibration mode to improve the estimate of the crosstalk removal function.

Abstract translation: 用于从具有第一和第二（例如左和右）通道的系统（例如音频系统）去除串扰的技术。 在一个方面，在校准模式期间对相应的第一和第二放大器的第一和第二输出电压进行采样，其中放大器之一以参考电压驱动，另一个放大器的输出被配置为具有高 阻抗。 采样的第一和第二输出电压可被数字化以供处理器处理以估计串扰消除功能。 然后可以将串扰消除功能与输入信号相乘，并且在放大之前以交叉通道方式添加到第一和第二输入信号以从系统中去除串扰。 在某些方面，可以在校准模式期间施加多个参考电压以改善串扰消除功能的估计。

公开(公告)号：US08143952B2

公开(公告)日：2012-03-27

申请号：US12576033

申请日：2009-10-08

Applicant: Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

Inventor： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

IPC: H03F3/14

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F19/04 ,  H01F2017/002 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2924/3011

Abstract: A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.

Abstract translation: 公开了三维片上电感器，变压器和射频放大器。 射频放大器包括一对变压器和晶体管。 变压器包括至少两个电感耦合电感器。 电感器包括第一金属层的多个段，第二金属层的多个段，第一电感器输入端，第二电感器输入端和耦合第一金属层的多个段的多个穿通硅通孔 以及第二金属层的多个段，以在第一电感器输入端和第二电感器输入端之间形成连续的，不相交的路径。 电感器可以具有对称或不对称的几何形状。 第一金属层可以是芯片的后端部分中的金属层。 第二金属层可以位于芯片的再分布设计层中。

公开(公告)号：US6134430A

公开(公告)日：2000-10-17

申请号：US987853

申请日：1997-12-09

Applicant: Saed G. Younis ,  Seyfollah S. Bazarjani ,  Steven C. Ciccarelli

Inventor： Saed G. Younis ,  Seyfollah S. Bazarjani ,  Steven C. Ciccarelli

IPC: H03M1/18 ,  H03M3/02 ,  H04B1/10 ,  H04B1/16

CPC classification number: H04B1/1027 ,  H03M3/488 ,  H04B1/109 ,  H03M3/404 ,  H03M3/414

Abstract: A programmable dynamic range receiver which provides the requisite level of performance at reduced power consumption. The .SIGMA..DELTA. ADC within the receiver is designed with one or more loops. Each loop provides a predetermined dynamic range performance. The loops can be enabled or disabled based on the required dynamic range and a set of dynamic range thresholds. The .SIGMA..DELTA. ADC is also designed with adjustable bias current. The dynamic range of the .SIGMA..DELTA. ADC varies approximately proportional to the bias current. By adjusting the bias current, the required dynamic range can be provided by the .SIGMA..DELTA. ADC with minimal power consumption. A reference voltage of the .SIGMA..DELTA. ADC can be descreased when high dynamic range is not required, thereby allowing for less bias current in the .SIGMA..DELTA. ADC and supporting circuitry. The dynamic range of the .SIGMA..DELTA. ADC is a also function of the oversampling ratio which is proportional to the sampling frequency. High dynamic range requires a high oversampling ratio. When high dynamic range is not required, the sampling frequency can be lowered.

Abstract translation: 可编程动态范围接收器，以降低功耗提供必要的性能水平。 接收机内的SIGMA DELTA ADC设计有一个或多个回路。 每个循环提供预定的动态范围性能。 可以根据所需的动态范围和一组动态范围阈值启用或禁用这些循环。 SIGMA DELTA ADC还设计有可调偏置电流。 SIGMA DELTA ADC的动态范围与偏置电流大致成正比。 通过调整偏置电流，所需的动态范围可由SIGMA DELTA ADC提供，功耗最小。 当不需要高动态范围时，可以降低SIGMA DELTA ADC的参考电压，从而在SIGMA DELTA ADC和支持电路中允许更少的偏置电流。 SIGMA DELTA ADC的动态范围也是与采样频率成比例的过采样比的函数。 高动态范围需要高过采样比。 当不需要高动态范围时，可以降低采样频率。

公开(公告)号：US6005506A

公开(公告)日：1999-12-21

申请号：US987306

申请日：1997-12-09

Applicant: Seyfollah S. Bazarjani ,  Steven C. Ciccarelli ,  Saed G. Younis ,  Daniel K. Butterfield

Inventor： Seyfollah S. Bazarjani ,  Steven C. Ciccarelli ,  Saed G. Younis ,  Daniel K. Butterfield

IPC: H03M1/66 ,  H03D3/00 ,  H03D7/16 ,  H03M3/02 ,  H04B1/26 ,  H03M3/00 ,  H03K9/06

CPC classification number: H04B1/0032 ,  H03D3/007 ,  H03D7/165 ,  H04B1/0003 ,  H04B1/0039 ,  H04B1/26

Abstract: A receiver comprising a sigma-delta analog-to-digital converter (.SIGMA..DELTA. ADC) can be utilized in one of four configurations, as a subsampling bandpass receiver, a subsampling baseband receiver, a Nyquist sampling bandpass receiver, or a Nyquist sampling baseband receiver. For subsampling .SIGMA..DELTA. receivers, the sampling frequency is less than twice the center frequency of the input signal into the .SIGMA..DELTA. ADC. For Nyquist sampling .SIGMA..DELTA. receivers, the sampling frequency is at least twice the highest frequency of the input signal into the .SIGMA..DELTA. ADC. For baseband .SIGMA..DELTA. receivers, the center frequency of the output signal from the .SIGMA..DELTA. ADC is approximately zero or DC. For bandpass .SIGMA..DELTA. receivers, the center frequency of the output signal from the .SIGMA..DELTA. ADC is greater than zero. The sampling frequency can be selected based on the bandwidth of the input signal to simplify the design of the digital circuits used to process the output samples from the .SIGMA..DELTA. ADC. Furthermore, the center frequency of the input signal can be selected based on the sampling frequency and the bandwidth of the input signal. The .SIGMA..DELTA. ADC within the receiver provides many benefits.

Abstract translation: 包括Σ-Δ模数转换器（SIGMA DELTA ADC）的接收机可以用于四种配置中的一种，作为子采样带通接收机，子采样基带接收机，奈奎斯特采样带通接收机或奈奎斯特采样基带接收机 。 对于子采样SIGMA DELTA接收机，采样频率小于进入SIGMA DELTA ADC的输入信号的中心频率的两倍。 对于奈奎斯特采样SIGMA DELTA接收机，采样频率至少是SIGMA DELTA ADC输入信号的最高频率的两倍。 对于基带SIGMA DELTA接收机，来自SIGMA DELTA ADC的输出信号的中心频率大约为零或DC。 对于带通SIGMA DELTA接收机，来自SIGMA DELTA ADC的输出信号的中心频率大于零。 可以根据输入信号的带宽选择采样频率，以简化用于处理SIGMA DELTA ADC的输出采样的数字电路的设计。 此外，可以基于输入信号的采样频率和带宽来选择输入信号的中心频率。 接收机内的SIGMA DELTA ADC提供了许多好处。

公开(公告)号：US20120056680A1

公开(公告)日：2012-03-08

申请号：US13294351

申请日：2011-11-11

Applicant: Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

Inventor： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

IPC: H03F3/16

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F19/04 ,  H01F2017/002 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2924/3011

Abstract: A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.

Abstract translation: 公开了一种三维片上射频放大器，其包括第一和第二变压器和第一晶体管。 第一变压器包括第一和第二电感耦合电感器。 第二变压器包括第三和第四电感耦合电感器。 每个电感器包括在第一金属层中的多个第一段; 第二金属层中的多个第二段; 第一和第二输入以及耦合第一和第二段的多通孔，以形成第一和第二输入之间的连续路径。 第一电感器的第一输入耦合到放大器输入端; 第二电感器的第一输入耦合到第一晶体管栅极; 第三电感器的第一输入耦合到第一晶体管漏极，第四电感器的第一输入耦合到放大器输出端。 第二电感器输入和第一晶体管源耦合到地。

公开(公告)号：US6137321A

公开(公告)日：2000-10-24

申请号：US228826

申请日：1999-01-12

Applicant: Seyfollah S. Bazarjani

Inventor： Seyfollah S. Bazarjani

IPC: G11C27/02 ,  H03K17/00

CPC classification number: G11C27/026

Abstract: A linear switch is incorporated into an active sample and hold switch. The active sample and hold circuit is symmetric and configured to accept a balanced input. Two linear switches couple a positive input signal of the balanced input to two different sampling capacitors. After the sampling capacitors are charged, another set of switches configures the sampling capacitors such that one of the sampling capacitor is in the feed back of an op amp and the other is connected from the input of the op amp to ground. In this configuration, the circuit has a gain of two and the output of the op amp is twice the voltage sampled by the sampling capacitors.

Abstract translation: 线性开关并入有源采样保持开关。 有源采样和保持电路是对称的并且被配置为接受平衡输入。 两个线性开关将平衡输入的正输入信号耦合到两个不同的采样电容。 在采样电容器充电之后，另一组开关配置采样电容器，使得采样电容器中的一个位于运算放大器的反馈中，另一组从运算放大器的输入端连接到地。 在这种配置中，电路增益为2，运算放大器的输出为采样电容采样电压的两倍。

公开(公告)号：US08508301B2

公开(公告)日：2013-08-13

申请号：US13294351

申请日：2011-11-11

Applicant: Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

Inventor： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

IPC: H03F3/14

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F19/04 ,  H01F2017/002 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2924/3011

Abstract: A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.

Abstract translation: 公开了一种三维片上射频放大器，其包括第一和第二变压器和第一晶体管。 第一变压器包括第一和第二电感耦合电感器。 第二变压器包括第三和第四电感耦合电感器。 每个电感器包括在第一金属层中的多个第一段; 第二金属层中的多个第二段; 第一和第二输入以及耦合第一和第二段的多通孔，以形成第一和第二输入之间的连续路径。 第一电感器的第一输入耦合到放大器输入端; 第二电感器的第一输入耦合到第一晶体管栅极; 第三电感器的第一输入耦合到第一晶体管漏极，第四电感器的第一输入耦合到放大器输出端。 第二电感器输入和第一晶体管源耦合到地。

公开(公告)号：US20110084765A1

公开(公告)日：2011-04-14

申请号：US12576033

申请日：2009-10-08

Applicant: Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

Inventor： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

IPC: H03F3/16 ,  H01F5/00

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F19/04 ,  H01F2017/002 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2924/3011

Abstract: A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.

Abstract translation: 公开了三维片上电感器，变压器和射频放大器。 射频放大器包括一对变压器和晶体管。 变压器包括至少两个电感耦合电感器。 电感器包括第一金属层的多个段，第二金属层的多个段，第一电感器输入端，第二电感器输入端和耦合第一金属层的多个段的多个穿通硅通孔 以及第二金属层的多个段，以在第一电感器输入端和第二电感器输入端之间形成连续的，不相交的路径。 电感器可以具有对称或不对称的几何形状。 第一金属层可以是芯片的后端部分中的金属层。 第二金属层可以位于芯片的再分布设计层中。

公开(公告)号：US06215337B1

公开(公告)日：2001-04-10

申请号：US09228827

申请日：1999-01-12

Applicant: Seyfollah S. Bazarjani

Inventor： Seyfollah S. Bazarjani

IPC: G11C2702

CPC classification number: G11C27/02 ,  H03K17/145 ,  H03K17/162 ,  H03K17/6872

Abstract: A linear sampling circuit is constructed with an p-channel and an n-channel field effect transistor (FET). A source node of the p-channel FET is coupled to a drain node of the n-channel FET and a drain node of the p-channel FET is coupled to a source node of the n-channel FET. A sampling clock is coupled to the gate node of each FET. A first side of the linear sampling circuit is connected to an analog or RF signal source and a far side of the linear sampling circuit is connected to a holding capacitor. The a n-channel FET has a n-channel width. A p-channel FET has a p-channel width. The p-channel width is larger than the n-channel width in order to increase the linearity of the on-resistance of the resulting switch.

Abstract translation: 线性采样电路由p沟道和n沟道场效应晶体管（FET）构成。 p沟道FET的源节点耦合到n沟道FET的漏极节点，并且p沟道FET的漏极节点耦合到n沟道FET的源极节点。 采样时钟耦合到每个FET的栅极节点。 线性采样电路的第一侧连接到模拟或RF信号源，线性采样电路的远端连接到保持电容器。 n沟道FET具有n沟道宽度。 p沟道FET具有p沟道宽度。 p沟道宽度大于n沟道宽度，以增加所得开关的导通电阻的线性度。