知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.011 seconds)

    Level shift circuit and power conversion unit
    1.
    发明授权
    Level shift circuit and power conversion unit 有权
    电平移位电路和电源转换单元

    公开(公告)号：US08299836B2

    公开(公告)日：2012-10-30

    申请号：US13029341

    申请日：2011-02-17

    Applicant: Naoki Sakurai ,  Junichi Sakano ,  Seigoh Yukutake

    Inventor： Naoki Sakurai ,  Junichi Sakano ,  Seigoh Yukutake

    IPC: H03L5/00

    CPC classification number: H03K19/0175

    Abstract: In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.

    Abstract translation: 在电平移位电路中，当高电压侧的电源电压变化dV / dt发生并影响电路的逻辑电平时，在第一和第二逻辑电路中屏蔽并防止故障信号的通过 通过利用在设定侧和复位侧出现这种变化的事实，通过来自时间常数生成电路的信号或者预先发生电力电压变化的部分。 当在高电压侧产生电源电压变化dV / dt时，在该掩蔽的定时中的充分允许阻止了错误的信号被发送到触发器，并且控制信号从低电压侧电路 即使在半导体工艺中的每个元件存在生产变化时，也不会对高压侧电路产生故障。

    LEVEL SHIFT CIRCUIT AND POWER CONVERSION UNIT
    2.
    发明申请
    LEVEL SHIFT CIRCUIT AND POWER CONVERSION UNIT 有权
    电平转换电路和电源转换单元

    公开(公告)号：US20110227626A1

    公开(公告)日：2011-09-22

    申请号：US13029341

    申请日：2011-02-17

    Applicant: Naoki SAKURAI ,  Junichi Sakano ,  Seigoh Yukutake

    Inventor： Naoki SAKURAI ,  Junichi Sakano ,  Seigoh Yukutake

    IPC: H03L5/00

    CPC classification number: H03K19/0175

    Abstract: In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.

    Abstract translation: 在电平移位电路中，当高电压侧的电源电压变化dV / dt发生并影响电路的逻辑电平时，在第一和第二逻辑电路中屏蔽并防止故障信号的通过 通过利用在设定侧和复位侧出现这种变化的事实，通过来自时间常数生成电路的信号或者预先发生电力电压变化的部分。 当在高电压侧产生电源电压变化dV / dt时，在该掩蔽的定时中的充分允许阻止了错误的信号被发送到触发器，并且控制信号从低电压侧电路 即使在半导体工艺中的每个元件存在生产变化时，也不会对高压侧电路产生故障。

    Synchronous memory with pipelined write operation
    6.
    发明授权
    Synchronous memory with pipelined write operation 失效
    具有流水线写入操作的同步存储器

    公开(公告)号：US5761150A

    公开(公告)日：1998-06-02

    申请号：US651873

    申请日：1996-05-21

    Applicant: Seigoh Yukutake ,  Kinya Mitsumoto ,  Takashi Akioka ,  Masahiro Iwamura ,  Noboru Akiyama

    Inventor： Seigoh Yukutake ,  Kinya Mitsumoto ,  Takashi Akioka ,  Masahiro Iwamura ,  Noboru Akiyama

    IPC: G11C11/413 ,  G06F12/00 ,  G11C7/10 ,  G11C8/06 ,  G11C11/401 ,  G11C11/407 ,  G11C11/418 ,  G11C8/00 ,  G11C7/00

    CPC classification number: G11C8/06 ,  G11C11/418 ,  G11C7/1072 ,  G11C2207/2218

    Abstract: There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.

    Abstract translation: 提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。 为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。 中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。 选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。

    Memory circuit improved in electrical characteristics
    9.
    发明授权
    Memory circuit improved in electrical characteristics 失效
    存储器电路改善了电气特性

    公开(公告)号：US5742551A

    公开(公告)日：1998-04-21

    申请号：US463851

    申请日：1995-06-05

    Applicant: Seigoh Yukutake ,  Yutaka Kobayashi ,  Takashi Akioka ,  Masahiro Iwamura

    Inventor： Seigoh Yukutake ,  Yutaka Kobayashi ,  Takashi Akioka ,  Masahiro Iwamura

    IPC: H03F3/72 ,  H03K17/62 ,  G11C7/02

    CPC classification number: H03F3/72 ,  H03K17/6264 ,  H03F2203/7203

    Abstract: A constant current source is connected in series to a current source circuit including a MOS transistor which is used as a current source for a differential output amplifier circuit, an emitter follower circuit or a source follower circuit used with a semiconductor integrated circuit. In a multiplex circuit, an input signal is inputted to each of base terminals of a plurality of bipolar transistors. When one input signal is selected, the bipolar transistor corresponding to the selected input signal is made to be operable with an input signal from a signal input terminal by a control circuit. The bipolar transistors corresponding to the non-selection input signals are turned OFF irrespective of potential levels of the individual input signals by current drawing circuits. There is also disclosed a semiconductor memory circuit having a plurality of memory cells, a memory cell selection scheme and a sense amplifier for amplifying data outputted from the selected memory cell, in which a constant current circuit is provided in series connection to the sense amplifier to enhance the performance characteristics of the memory circuit. Also, a plural memory array scheme is disclosed which employs multiplexing techniques connected to presense amplifier circuits of the respective memory arrays.

    Abstract translation: 恒流源串联连接到电流源电路，该电流源电路包括用作差分输出放大器电路的电流源的MOS晶体管，射极跟随器电路或与半导体集成电路一起使用的源极跟随器电路。 在复用电路中，输入信号被输入到多个双极晶体管的每个基极端子。 当选择一个输入信号时，与所选择的输入信号相对应的双极晶体管可以通过控制电路与来自信号输入端的输入信号一起工作。 对应于非选择输入信号的双极晶体管截止，而与当前绘图电路的各个输入信号的电位电平无关。 还公开了具有多个存储单元的半导体存储器电路，存储单元选择方案和用于放大从所选择的存储单元输出的数据的读出放大器，其中恒定电流电路与读出放大器串联连接， 提高存储电路的性能特点。 此外，公开了一种多重存储器阵列方案，其采用连接到相应存储器阵列的预放大器电路的复用技术。

Patent Agency Ranking