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    Methods of Fabricating High Voltage MOSFET Having Doped Buried Layer
    2.
    发明申请
    Methods of Fabricating High Voltage MOSFET Having Doped Buried Layer 失效
    制造具有掺杂埋层的高压MOSFET的方法

    公开(公告)号：US20070105298A1

    公开(公告)日：2007-05-10

    申请号：US11620091

    申请日：2007-01-05

    申请人： Sun-hak Lee ,  Kwang-dong Yoo

    发明人： Sun-hak Lee ,  Kwang-dong Yoo

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/66613 ,  H01L29/1083 ,  H01L29/7833

    摘要： A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region. The well region extends opposite the insulated gate electrode and has a sufficient width that dopants therein partially compensate innermost portions of the lightly doped source and drain extensions that extend underneath the insulated gate electrode. However, the well region is not so wide as to provide compensation to remaining portions of the lightly doped source and drain extensions or the source and drain contact regions.

    摘要翻译： MOSFET在半导体衬底的表面上具有绝缘栅电极，其中具有第一导电类型的杂质区延伸到表面。 第二导电类型的源区和漏区设置在杂质区中。 源极区域包括延伸到表面的高掺杂源极接合区域和轻掺杂源极延伸部分。 轻掺杂源极延伸部在绝缘栅电极的第一端下方横向延伸，并且与阱区域限定源极侧P-N结。 漏极区域包括延伸到表面的高度掺杂的漏极接触区域和轻掺杂漏极延伸部分。 轻掺杂的漏极延伸部在绝缘栅电极的第二端下方横向延伸，并且与阱区域限定漏极侧P-N结。 在杂质区域内延伸并且与其限定非整流结的阱区域比杂质区域更高掺杂。 阱区域与绝缘栅电极相对延伸并且具有足够的宽度，其中的掺杂剂部分地补偿在绝缘栅电极下方延伸的轻掺杂源极和漏极延伸部分的最内部分。 然而，阱区域不是如此宽，以便为轻掺杂源极和漏极延伸部分或源极和漏极接触区域的剩余部分提供补偿。

    High voltage MOSFET having doped buried layer
    3.
    发明授权
    High voltage MOSFET having doped buried layer 失效
    具有掺杂埋层的高压MOSFET

    公开(公告)号：US07176538B2

    公开(公告)日：2007-02-13

    申请号：US10860295

    申请日：2004-06-03

    申请人： Sun-hak Lee ,  Kwang-dong Yoo

    发明人： Sun-hak Lee ,  Kwang-dong Yoo

    IPC分类号： H01L29/772

    CPC分类号： H01L29/66613 ,  H01L29/1083 ,  H01L29/7833

    摘要： A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region. The well region extends opposite the insulated gate electrode and has a sufficient width that dopants therein partially compensate innermost portions of the lightly doped source and drain extensions that extend underneath the insulated gate electrode. However, the well region is not so wide as to provide compensation to remaining portions of the lightly doped source and drain extensions or the source and drain contact regions.

    摘要翻译： MOSFET在半导体衬底的表面上具有绝缘栅电极，其中具有第一导电类型的杂质区延伸到表面。 第二导电类型的源区和漏区设置在杂质区中。 源极区域包括延伸到表面的高掺杂源极接合区域和轻掺杂源极延伸部分。 轻掺杂源极延伸部在绝缘栅电极的第一端下方横向延伸，并且与阱区域限定源极侧P-N结。 漏极区域包括延伸到表面的高度掺杂的漏极接触区域和轻掺杂漏极延伸部分。 轻掺杂的漏极延伸部在绝缘栅电极的第二端下方横向延伸，并且与阱区域限定漏极侧P-N结。 在杂质区域内延伸并且与其限定非整流结的阱区域比杂质区域更高掺杂。 阱区域与绝缘栅电极相对延伸并且具有足够的宽度，其中的掺杂剂部分地补偿在绝缘栅电极下方延伸的轻掺杂源极和漏极延伸部分的最内部分。 然而，阱区域不是如此宽，以便为轻掺杂源极和漏极延伸部分或源极和漏极接触区域的剩余部分提供补偿。

    Semiconductor device and method of fabricating the same
    4.
    发明申请
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20100207204A1

    公开(公告)日：2010-08-19

    申请号：US12656671

    申请日：2010-02-12

    申请人： Young-Mok Kim ,  Sun-Hak Lee ,  Tae-Cheol Lee ,  Yong-Sang Jeong

    发明人： Young-Mok Kim ,  Sun-Hak Lee ,  Tae-Cheol Lee ,  Yong-Sang Jeong

    IPC分类号： H01L29/78

    CPC分类号： H01L29/4236 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/1037 ,  H01L29/7834

    摘要： A semiconductor device comprises a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer.

    摘要翻译： 半导体器件包括衬底中的凹槽，栅极绝缘层包括第一部分和第二部分，第一部分具有第一厚度并覆盖凹槽的侧壁的下部和凹槽的底表面， 并且所述第二部分具有第二厚度并且覆盖所述凹槽的侧壁的上部，所述第二厚度大于所述第一厚度，填充所述凹陷沟槽的栅电极，具有第一浓度的第一杂质区域并且设置在相对的位置 栅极电极的侧面，以及具有大于第一浓度的第二浓度的第二杂质区域，并且设置在第一杂质区域上以对应于栅极绝缘层的第二部分。

    High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same
    5.
    发明授权
    High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same 有权
    高频MOS晶体管，其形成方法以及制造其的半导体器件的制造方法

    公开(公告)号：US07618854B2

    公开(公告)日：2009-11-17

    申请号：US12032377

    申请日：2008-02-15

    申请人： Sun-Hak Lee

    发明人： Sun-Hak Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/66659 ,  H01L29/7835

    摘要： In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.

    摘要翻译： 在高频LDMOS晶体管中，在衬底上形成栅极结构。 在与栅极结构间隔开的衬底上形成以第一浓度掺杂第一类型杂质的漏极。 掺杂有低于第一浓度的第二浓度的第一种杂质的缓冲阱包围漏极的侧部和下部。 在缓冲阱和栅极结构之间形成掺杂有低于第二浓度的第三浓度的第一种杂质的轻掺杂漏极。 掺杂有第一浓度的第一类型杂质的源极相对于栅极结构形成在与栅极结构相邻并且与漏极相对的衬底上。 因此，在不增加栅极结构和漏极之间的电容的情况下，导通电阻随着LDMOS晶体管中的击穿电压增加而减小。

    Method of manufacturing a semiconductor device
    6.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US5913114A

    公开(公告)日：1999-06-15

    申请号：US7534

    申请日：1998-01-15

    申请人： Sun-Hak Lee ,  Chang-Ki Jeon ,  Cheol-Joong Kim

    发明人： Sun-Hak Lee ,  Chang-Ki Jeon ,  Cheol-Joong Kim

    IPC分类号： H01L27/06 ,  H01L21/8249 ,  H01L21/8238

    CPC分类号： H01L29/66712 ,  H01L21/8249 ,  H01L29/7809 ,  H01L29/42368

    摘要： A semiconductor device, and a method of manufacturing the same, containing a high voltage DMOS transistor, a low voltage CMOS transistor, and a bipolar transistor in a single substrate. The steps include forming an isolation layer within the substrate in an isolation region between each of a DMOS region, a CMOS region, or a bipolar region. A first oxide layer of variable thickness is formed on the substrate, a thick second oxide layer is formed on the isolation layer, and a polysilicon layer is formed on both oxide layers. The polysilicon layer is patterned to form gate patterns on the first oxide layer and resistive patterns on the second oxide layer. The gate pattern is then doped but the resistive pattern is undoped. The thickness of the first oxide layer in the DMOS region is greater than the thickness of the first oxide layer in the CMOS region.

    摘要翻译： 在单个基板中包含高电压DMOS晶体管，低电压CMOS晶体管和双极晶体管的半导体器件及其制造方法。 这些步骤包括在DMOS区域，CMOS区域或双极区域中的每一个之间的隔离区域内在衬底内形成隔离层。 在衬底上形成可变厚度的第一氧化物层，在隔离层上形成厚的第二氧化物层，并且在两个氧化物层上形成多晶硅层。 图案化多晶硅层以在第一氧化物层上形成栅极图案，并在第二氧化物层上形成电阻图案。 然后掺杂栅极图案，但是电阻图案是未掺杂的。 DMOS区域中的第一氧化物层的厚度大于CMOS区域中第一氧化物层的厚度。

    MOS transistor and fabrication method thereof
    8.
    发明授权
    MOS transistor and fabrication method thereof 失效
    MOS晶体管及其制造方法

    公开(公告)号：US06853040B2

    公开(公告)日：2005-02-08

    申请号：US10300293

    申请日：2002-11-20

    申请人： Kyung-Oun Jang ,  Sun-Hak Lee

    发明人： Kyung-Oun Jang ,  Sun-Hak Lee

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

    CPC分类号： H01L29/7816 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7835

    摘要： A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region. P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

    摘要翻译： 提供具有相对高的击穿电压的CMOS晶体管。 CMOS晶体管包括在P型衬底上的N型外延层。 在衬底和外延层之间是重掺杂的N型掩埋层和重掺杂的P型基极层。 N型接收区域靠近NMOS区域的边缘，并且在阱区域包围的区域中是双阱。 在各孔中形成N +源极和漏极区。 当漏极区域插入在漏极和隔离区域之间时，当施加高电压时，在漏极和隔离区域之间发生击穿。 在PMOS区域也形成双阱。 在各个孔中形成P +源极和漏极区。 当N型阱围绕源区和体区时，当施加高电压时，在掩埋区和隔离区之间发生击穿。

    High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same
    9.
    发明申请
    High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same 审中-公开

    公开(公告)号：US20060011981A1

    公开(公告)日：2006-01-19

    申请号：US11181395

    申请日：2005-07-14

    申请人： Sun-Hak Lee

    发明人： Sun-Hak Lee

    IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/66659 ,  H01L29/7835

    摘要： In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.

    MOS transistor and fabrication method thereof
    10.
    发明授权
    MOS transistor and fabrication method thereof 有权
    MOS晶体管及其制造方法

    公开(公告)号：US06507080B2

    公开(公告)日：2003-01-14

    申请号：US09761902

    申请日：2001-01-17

    申请人： Kyung-Oun Jang ,  Sun-Hak Lee

    发明人： Kyung-Oun Jang ,  Sun-Hak Lee

    IPC分类号： H01L2972

    CPC分类号： H01L29/7816 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7835

    摘要： A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

    摘要翻译： 提供具有相对高的击穿电压的CMOS晶体管。 CMOS晶体管包括在P型衬底上的N型外延层。 在衬底和外延层之间是重掺杂的N型掩埋层和重掺杂的P型基极层。 N型接收区靠近NMOS区域的边缘，并且双阱位于被宿区域包围的区域中。 在各孔中形成N +源极和漏极区。 当漏极区域插入在漏极和隔离区域之间时，当施加高电压时，在漏极和隔离区域之间发生击穿。 双阱也形成在PMOS区P +源极和漏极区形成在相应的阱中。 当N型阱围绕源区和体区时，当施加高电压时，在掩埋区和隔离区之间发生击穿。