公开(公告)号：US20070105298A1

公开(公告)日：2007-05-10

申请号：US11620091

申请日：2007-01-05

申请人： Sun-hak Lee ,  Kwang-dong Yoo

发明人： Sun-hak Lee ,  Kwang-dong Yoo

IPC分类号： H01L21/8234

CPC分类号： H01L29/66613 ,  H01L29/1083 ,  H01L29/7833

摘要： A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region. The well region extends opposite the insulated gate electrode and has a sufficient width that dopants therein partially compensate innermost portions of the lightly doped source and drain extensions that extend underneath the insulated gate electrode. However, the well region is not so wide as to provide compensation to remaining portions of the lightly doped source and drain extensions or the source and drain contact regions.

摘要翻译： MOSFET在半导体衬底的表面上具有绝缘栅电极，其中具有第一导电类型的杂质区延伸到表面。 第二导电类型的源区和漏区设置在杂质区中。 源极区域包括延伸到表面的高掺杂源极接合区域和轻掺杂源极延伸部分。 轻掺杂源极延伸部在绝缘栅电极的第一端下方横向延伸，并且与阱区域限定源极侧P-N结。 漏极区域包括延伸到表面的高度掺杂的漏极接触区域和轻掺杂漏极延伸部分。 轻掺杂的漏极延伸部在绝缘栅电极的第二端下方横向延伸，并且与阱区域限定漏极侧P-N结。 在杂质区域内延伸并且与其限定非整流结的阱区域比杂质区域更高掺杂。 阱区域与绝缘栅电极相对延伸并且具有足够的宽度，其中的掺杂剂部分地补偿在绝缘栅电极下方延伸的轻掺杂源极和漏极延伸部分的最内部分。 然而，阱区域不是如此宽，以便为轻掺杂源极和漏极延伸部分或源极和漏极接触区域的剩余部分提供补偿。

公开(公告)号：US07176538B2

公开(公告)日：2007-02-13

申请号：US10860295

申请日：2004-06-03

申请人： Sun-hak Lee ,  Kwang-dong Yoo

发明人： Sun-hak Lee ,  Kwang-dong Yoo

IPC分类号： H01L29/772

CPC分类号： H01L29/66613 ,  H01L29/1083 ,  H01L29/7833

摘要： A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region. The well region extends opposite the insulated gate electrode and has a sufficient width that dopants therein partially compensate innermost portions of the lightly doped source and drain extensions that extend underneath the insulated gate electrode. However, the well region is not so wide as to provide compensation to remaining portions of the lightly doped source and drain extensions or the source and drain contact regions.

摘要翻译： MOSFET在半导体衬底的表面上具有绝缘栅电极，其中具有第一导电类型的杂质区延伸到表面。 第二导电类型的源区和漏区设置在杂质区中。 源极区域包括延伸到表面的高掺杂源极接合区域和轻掺杂源极延伸部分。 轻掺杂源极延伸部在绝缘栅电极的第一端下方横向延伸，并且与阱区域限定源极侧P-N结。 漏极区域包括延伸到表面的高度掺杂的漏极接触区域和轻掺杂漏极延伸部分。 轻掺杂的漏极延伸部在绝缘栅电极的第二端下方横向延伸，并且与阱区域限定漏极侧P-N结。 在杂质区域内延伸并且与其限定非整流结的阱区域比杂质区域更高掺杂。 阱区域与绝缘栅电极相对延伸并且具有足够的宽度，其中的掺杂剂部分地补偿在绝缘栅电极下方延伸的轻掺杂源极和漏极延伸部分的最内部分。 然而，阱区域不是如此宽，以便为轻掺杂源极和漏极延伸部分或源极和漏极接触区域的剩余部分提供补偿。

公开(公告)号：US07446000B2

公开(公告)日：2008-11-04

申请号：US11826714

申请日：2007-07-18

申请人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

发明人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823857 ,  H01L21/82385 ,  H01L21/823892

摘要： A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

摘要翻译： 可以提供制造包括具有不同厚度的栅极电介质的半导体器件的方法。 制造半导体器件的方法可以包括提供具有较高电压器件区域和较低电压器件区域的衬底，在衬底上形成抗氧化层，并选择性地去除衬底上的抗氧化层的部分。 该方法还可以包括在衬底上进行第一热氧化以在抗氧化层的选择性去除的部分上形成场氧化物层，去除设置在较高电压器件区上的抗氧化层，进行第二热氧化 在所述衬底上形成在所述较高电压器件区域上的中央较高电压栅极氧化物层，去除设置在所述较低电压器件区域上的所述抗氧化层，并在所述衬底上进行第三热氧化以形成低电压栅极氧化物层 在较低电压器件区域。

公开(公告)号：US07381621B2

公开(公告)日：2008-06-03

申请号：US11620091

申请日：2007-01-05

申请人： Sun-hak Lee ,  Kwang-dong Yoo

发明人： Sun-hak Lee ,  Kwang-dong Yoo

IPC分类号： H01L21/336

CPC分类号： H01L29/66613 ,  H01L29/1083 ,  H01L29/7833

摘要： A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region. The well region extends opposite the insulated gate electrode and has a sufficient width that dopants therein partially compensate innermost portions of the lightly doped source and drain extensions that extend underneath the insulated gate electrode. However, the well region is not so wide as to provide compensation to remaining portions of the lightly doped source and drain extensions or the source and drain contact regions.

摘要翻译： MOSFET在半导体衬底的表面上具有绝缘栅电极，其中具有第一导电类型的杂质区延伸到表面。 第二导电类型的源区和漏区设置在杂质区中。 源极区域包括延伸到表面的高掺杂源极接合区域和轻掺杂源极延伸部分。 轻掺杂源极延伸部在绝缘栅电极的第一端下方横向延伸，并且与阱区域限定源极侧P-N结。 漏极区域包括延伸到表面的高度掺杂的漏极接触区域和轻掺杂漏极延伸部分。 轻掺杂的漏极延伸部在绝缘栅电极的第二端下方横向延伸，并且与阱区域限定漏极侧P-N结。 在杂质区域内延伸并且与其限定非整流结的阱区域比杂质区域更高掺杂。 阱区域与绝缘栅电极相对延伸并且具有足够的宽度，其中的掺杂剂部分地补偿在绝缘栅电极下方延伸的轻掺杂源极和漏极延伸部分的最内部分。 然而，阱区域不是如此宽，以便为轻掺杂源极和漏极延伸部分或源极和漏极接触区域的剩余部分提供补偿。

公开(公告)号：US20080124873A1

公开(公告)日：2008-05-29

申请号：US11826714

申请日：2007-07-18

申请人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

发明人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

IPC分类号： H01L21/8236

CPC分类号： H01L21/823857 ,  H01L21/82385 ,  H01L21/823892

摘要： A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.