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公开(公告)号：US5745427A
公开(公告)日：1998-04-28
申请号：US773706
申请日：1996-12-27
CPC分类号： G11C7/1072 , G11C7/1078
摘要： The present invention is an embedded random access memory device especially adapted for use with digital processors having a pipelined data architecture. In accordance with one embodiment of the present invention a write access cycle performed at a memory location within the memory device is phase shifted by one phase of a clock cycle relative an access cycle of a read operation. This is advantageous in that the integrity of data which traditionally would have been presented late in the write access cycle can still be maintained, since the entire write cycle is now shifted one phase later. A precharge signal which follows the write access is correspondingly shifted by one phase of a clock cycle. A wait state is inserted between the write access cycle and a read access cycle which directly follows in the same memory bank of the memory device. The wait state eliminates conflicts between the access cycle and the precharge cycle.
摘要翻译： 本发明是特别适用于具有流水线数据结构的数字处理器的嵌入式随机存取存储器件。 根据本发明的一个实施例，在存储器件内的存储器位置执行的写访问周期相对于读操作的访问周期相移一个时钟周期的一个相位。 这是有利的，因为传统上将在写访问周期中迟到的数据的完整性仍然可以被保持，因为整个写周期现在在一个阶段之后被移位。 在写访问之后的预充电信号相应地移位一个时钟周期的一个相位。 在写访问周期和直接跟随在存储器件的同一存储体中的读访问周期之间插入等待状态。 等待状态消除了访问周期和预充电周期之间的冲突。
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公开(公告)号：US07773667B2
公开(公告)日：2010-08-10
申请号：US11181286
申请日：2005-07-14
CPC分类号： G01R31/31715
摘要： The various embodiments of the invention provide an apparatus, system and method of asynchronous testing a serializer and deserializer data communication apparatus (SERDES) for determining frequency and phase locking to pseudo asynchronous input data having a continual phase offset. An exemplary apparatus includes a data sampler adapted to sample input serial data and to provide output data; a controlled tap delay with a selected tap having a phase offset from the input serial data, in which the selected tap is selectively coupleable to the data sampler to provide pseudo asynchronous input serial data; a first variable delay control adapted to delay a reference frequency provided to the controlled tap delay in response to the pseudo asynchronous input serial data; and a second delay control adapted to adjust the plurality of taps in response to the pseudo asynchronous input serial data. In additional embodiments, the pseudo asynchronous input serial data is provided from an interpolated phase from at least two selected taps.
摘要翻译： 本发明的各种实施例提供了用于确定频率和相位锁定到具有连续相位偏移的伪异步输入数据的串行器和解串器数据通信装置（SERDES）的异步测试的装置，系统和方法。 示例性装置包括适于对输入串行数据进行采样并提供输出数据的数据采样器; 具有与输入串行数据相位偏移的所选抽头的受控抽头延迟，其中所选择的抽头选择性地耦合到数据采样器以提供伪异步输入串行数据; 第一可变延迟控制器，其适于响应于所述伪异步输入串行数据延迟提供给受控抽头延迟的参考频率; 以及适于响应于所述伪异步输入串行数据来调整所述多个抽头的第二延迟控制。 在另外的实施例中，伪异步输入串行数据从来自至少两个选择的抽头的内插相位提供。
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公开(公告)号：US5828251A
公开(公告)日：1998-10-27
申请号：US674411
申请日：1996-07-02
CPC分类号： H03K17/223
摘要： An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied. However, the voltage on the node may not properly discharge in all cases during brief power interruptions. Therefore, to increase the reliability of the power-up detector, a discharge circuit is included to help ensure that the voltage sensed by the power supply voltage-sensing circuit is at the proper level when the power supply voltage drops below a given level. The discharge circuit comprises a first capacitor that turns on a node discharge transistor when the power supply voltage drops below the given level. To provide protection against false discharge, a second capacitor is optionally provided that prevents the discharge transistor from conducting during very brief power supply voltage interruptions. In a preferred embodiment, the second capacitor is effectively disabled at low power supply voltages. This facilitates conduction of the discharge transistor for power supply voltage interruptions resulting from slow changes (low slew rate) in the power supply voltage.
摘要翻译： 集成电路包括上电检测器电路，其包括在正常操作期间由电容器保持在充电状态的节点。 节点上的电压由感测电路感测，通常是在最初施加电力时产生上电复位脉冲的逆变器。 然而，在短暂的电源中断期间，节点上的电压在所有情况下可能无法正确放电。 因此，为了提高上电检测器的可靠性，包括放电电路以帮助确保当电源电压降低到给定电平以下时，由电源电压感测电路感测到的电压处于适当的电平。 放电电路包括当电源电压低于给定电平时接通节点放电晶体管的第一电容器。 为了提供防止假放电的保护，可选地提供第二电容器，其在非常短暂的电源电压中断期间防止放电晶体管导通。 在优选实施例中，第二电容器在低电源电压下被有效地禁用。 这有助于放电晶体管的导通，导致电源电压缓慢变化（低压摆率）导致的电源电压中断。
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公开(公告)号：US5991220A
公开(公告)日：1999-11-23
申请号：US37099
申请日：1998-03-09
CPC分类号： G11C17/18
摘要： Blowable fuses on an integrated circuit are programmed in software, responsive to the control of an addressable memory which communicates with the peripheral data bus of a digital processor to allow increased flexibility of the programming operation, and to allow for correction both during the manufacturing process and after packaging of the manufactured integrated circuit. In a preferred embodiment, the fuses are operated (i.e., blown) responsive to transistor switching elements present on the integrated circuit and which are controlled by the addressable memory. The switching elements, and the associated fuses, can be accessed through software in similar fashion to any other peripheral device. The preferred addressable memory includes an instruction register and a data register, which are loaded from and write to the peripheral data bus. Internally, the data register includes an array of registers corresponding to the fuse links with which the system is associated. Data words in the registers are written from or read to the data register tinder the control of instructions in the instruction register, and the fuses are then blown serially, by reference to the data in the registers.
摘要翻译： 集成电路中的可充电保险丝通过软件编程，响应于与数字处理器的外围数据总线进行通信的可寻址存储器的控制，以允许增加编程操作的灵活性，并允许在制造过程和 封装后制造的集成电路。 在优选实施例中，响应于存在于集成电路上并由可寻址存储器控制的晶体管开关元件，保险丝被操作（即，吹制）。 开关元件和相关保险丝可以通过与任何其他外围设备类似的方式通过软件访问。 优选的可寻址存储器包括指令寄存器和数据寄存器，其从外围数据总线加载并写入外围数据总线。 在内部，数据寄存器包括与系统相关联的熔丝链路对应的寄存器阵列。 寄存器中的数据字从数据寄存器中写入或读取，以控制指令寄存器中的指令，然后通过参考寄存器中的数据对熔丝进行串行写入。
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公开(公告)号：US5801558A
公开(公告)日：1998-09-01
申请号：US757059
申请日：1996-11-26
IPC分类号： H03K17/16 , H03K17/687 , H03K19/0175 , H03K19/0948
CPC分类号： H03K17/163
摘要： There is disclosed an integrated circuit includes an output driver circuit providing control of transition time from one state to another. The output driver includes first and second input transistors coupled to an input node at which data is received. First and second output transistors are coupled to an output node at which the data is presented when the output driver is enabled. The first input transistor is coupled to the first output transistor defining a first node. The second input transistor is coupled to the second output transistor defining a second node. First and second switching circuits are coupled between the first node and the second node. The first switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node. The first switching circuit exhibits a characteristic upon being switched from one of the first or second states to the other, such as from the first state to the second state, that impacts turn-on time of one of the first and second output transistors. The second switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node. The second switching circuit also exhibits a characteristic that upon being switched from one of the first and second states impacts turn-on time of the other of the first and second output transistors.
摘要翻译： 公开了一种集成电路，其包括输出驱动器电路，其提供从一个状态到另一个状态的转换时间的控制。 输出驱动器包括耦合到接收数据的输入节点的第一和第二输入晶体管。 第一和第二输出晶体管耦合到输出节点，在输出节点处，当输出驱动器被使能时，数据被呈现。 第一输入晶体管耦合到限定第一节点的第一输出晶体管。 第二输入晶体管耦合到限定第二节点的第二输出晶体管。 第一和第二开关电路耦合在第一节点和第二节点之间。 第一切换电路可以在将第一节点与第二节点隔离的第一状态和将第一节点耦合到第二节点的第二状态之间切换。 第一切换电路在从第一状态或第二状态之一转换为另一状态（例如从第一状态转换到第二状态时）具有影响第一和第二输出晶体管之一的导通时间的特性。 第二切换电路可以在将第一节点与第二节点隔离的第一状态和将第一节点耦合到第二节点的第二状态之间切换。 第二开关电路还具有当从第一和第二状态中的一个切换时影响第一和第二输出晶体管中的另一个的导通时间的特性。
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公开(公告)号：US5663677A
公开(公告)日：1997-09-02
申请号：US413527
申请日：1995-03-30
IPC分类号： H05K1/02 , H01L23/528 , H01L25/00
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： An improved integrated circuit conductor layout technique provides lower and upper conductor levels that bound circuit blocks and provide for power supply voltage distribution to the circuitry in the circuit blocks. The lower and upper conductor levels also provide for first and second groups of parallel signal conductors in wiring channels between circuit blocks. An intermediate conductor level is located between the lower and upper conductor levels, and conducts power supply voltages between adjacent circuit blocks. The power supply conductors formed in the intermediate conductor level also serve to isolate the signal conductors in the lower conductor level from the signal conductors in the upper conductor level (and vice-versa) in the wiring channel. This isolation typically improves the design of the integrated circuit by providing more reliable estimates of signal propagation in the wiring channels.
摘要翻译： 改进的集成电路导体布局技术提供了限制电路块的下层和上层导体电平，并为电路块中的电路提供电源电压分布。 下电极和上导体电平还为电路块之间的布线通道中的第一组和第二组并行信号导体提供。 中间导体电平位于下导体和上导体之间，并在相邻电路块之间传导电源电压。 形成在中间导体电平中的电源导体还用于将下导体电平中的信号导体与布线通道中的上导体电平（反之亦然）中的信号导线隔离开。 这种隔离通常通过在布线通道中提供更可靠的信号传播估计来改善集成电路的设计。
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7.发明授权
公开(公告)号：US06028756A
公开(公告)日：2000-02-22
申请号：US041543
申请日：1998-03-11
申请人： Ronald Lamar Freyman , Bruce Walter McNeill , Malcolm Harold Smith , Gary H. Weiss , Charles Raymond Miller
发明人： Ronald Lamar Freyman , Bruce Walter McNeill , Malcolm Harold Smith , Gary H. Weiss , Charles Raymond Miller
IPC分类号： H02H3/08 , H01L21/82 , H01L23/525 , H02H5/04 , H01L23/48
CPC分类号： H01L23/5256 , H01L2924/0002
摘要： An integrated circuit includes topological features for weakening or otherwise modifying a blowable fuse in order to decrease the current needed to blow the fuse. This allows a decrease in the size of the circuit components which are needed to supply the current for blowing the fuse, in turn allowing compaction of the layout of the circuitry needed to blow the fuse. To this end, topological features are used to deform the shape of or otherwise modify the fuse, in turn increasing the resistance of the fuse or introducing flaws that allow the fuse to blow at a lower current.
摘要翻译： 集成电路包括用于弱化或以其它方式修改可熔断熔断器的拓扑特征，以便降低熔断熔丝所需的电流。 这样可以减小为熔断器提供电流所需要的电路部件的尺寸，从而可以压缩熔断器所需电路的布局。 为此，拓扑特征用于使保险丝的形状变形或以其它方式修改保险丝，从而增加保险丝的电阻或引入漏电流，从而允许保险丝以较低电流吹动。
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公开(公告)号：US5646451A
公开(公告)日：1997-07-08
申请号：US486844
申请日：1995-06-07
申请人： Ronald Lamar Freyman , Craig Joseph Garen , Clinton Hays Holder, Jr. , Robert Nelson Kershaw , Edward Clayton Morgan
发明人： Ronald Lamar Freyman , Craig Joseph Garen , Clinton Hays Holder, Jr. , Robert Nelson Kershaw , Edward Clayton Morgan
IPC分类号： H01L23/495 , H01L23/50 , H01L21/60
CPC分类号： H01L23/50 , H01L23/4952 , H01L24/49 , H01L2223/6611 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L24/45 , H01L24/48 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/20106 , H01L2924/30107
摘要： A multifunctional chip includes first and second electrically isolated bonding pads. The chip also includes a control circuit coupled to the second bonding pad. The control circuit commands the chip to perform the first function if the first and second bonding pads are coupled. Alternatively, the control circuit commands the chip to perform the second function if the first and second bonding pads remain electrically isolated. The coupling or isolation between the first and second bonding pads is determined by wire bonds. Therefore, the use of wire bonds selects the function for the chip.
摘要翻译： 多功能芯片包括第一和第二电隔离的焊盘。 芯片还包括耦合到第二接合焊盘的控制电路。 如果第一和第二接合焊盘耦合，则控制电路命令芯片执行第一功能。 或者，如果第一和第二焊盘保持电隔离，则控制电路命令芯片执行第二功能。 第一和第二接合焊盘之间的耦合或隔离由引线键确定。 因此，使用引线键选择芯片的功能。
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