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公开(公告)号：US07863123B2
公开(公告)日：2011-01-04
申请号：US12355953
申请日：2009-01-19
申请人： Huiming Bu , Michael P. Chudzik , Ricardo A. Donaton , Naim Moumen , Hongwen Yan
发明人： Huiming Bu , Michael P. Chudzik , Ricardo A. Donaton , Naim Moumen , Hongwen Yan
IPC分类号： H01L21/336
CPC分类号： H01L29/4958 , H01L21/28079 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A low resistance contact is formed to a metal gate or a transistor including a High-κ gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.
摘要翻译： 低电阻触点形成于金属栅极或包括高电平的晶体管。 通过在栅极堆叠上施加衬垫，在栅极叠层之间施加填充材料，平坦化填充材料以支持高分辨率光刻，相互选择性地蚀刻填充材料和衬垫，从而在高集成度密度集成电路中形成栅极电介质 形成通孔并用金属，金属合金或诸如氮化钛的导电金属化合物填充通孔。
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2.发明申请METHOD FOR REMOVING THRESHOLD VOLTAGE ADJUSTING LAYER WITH EXTERNAL ACID DIFFUSION PROCESS 有权用外部酸性扩散过程去除阈值电压调节层的方法公开(公告)号：US20100330810A1
公开(公告)日：2010-12-30
申请号：US12490353
申请日：2009-06-24
申请人： Kuang-Jung Chen , Ricardo A. Donaton , Wu-Song Huang , Wai-Kin Li
发明人： Kuang-Jung Chen , Ricardo A. Donaton , Wu-Song Huang , Wai-Kin Li
IPC分类号： H01L21/31
CPC分类号： H01L21/31122 , H01L21/823842 , H01L21/823857
摘要： The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid.
摘要翻译： 本发明提供一种形成阈值电压调节的栅极叠层的方法，其中使用外部酸扩散工艺来从半导体衬底的一个器件区域选择性地去除一部分阈值电压调节层。 外部酸扩散方法使用酸性聚合物，其在烘烤时表现出酸浓度的增加，其可以扩散到阈值电压调节层的下部暴露部分。 扩散的酸与阈值电压调节层的暴露部分反应，提供酸反应层，与不暴露于扩散的酸的阈值电压调节层的横向相邻部分相比，可以选择性地除去酸反应层。
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公开(公告)号：US07615418B2
公开(公告)日：2009-11-10
申请号：US11380688
申请日：2006-04-28
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.
摘要翻译： 一种半导体结构和制造方法，更具体地说是具有嵌入在PFET的栅极和源极/漏极区域中的应力诱导材料的CMOS器件。 PFET区域和NFET区域具有不同尺寸的栅极，以改变NFET和PFET的器件性能。
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公开(公告)号：US08227870B2
公开(公告)日：2012-07-24
申请号：US13364564
申请日：2012-02-02
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823437 , H01L21/28088 , H01L27/0629 , H01L27/0802 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.
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5.发明授权Method for removing threshold voltage adjusting layer with external acid diffusion process 有权用外部酸性扩散法去除阈值电压调节层的方法公开(公告)号：US08227307B2
公开(公告)日：2012-07-24
申请号：US12490353
申请日：2009-06-24
申请人： Kuang-Jung Chen , Ricardo A. Donaton , Wu-Song Huang , Wai-Kin Li
发明人： Kuang-Jung Chen , Ricardo A. Donaton , Wu-Song Huang , Wai-Kin Li
IPC分类号： H01L21/8238 , H01L21/31
CPC分类号： H01L21/31122 , H01L21/823842 , H01L21/823857
摘要： The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid.
摘要翻译： 本发明提供一种形成阈值电压调节的栅极叠层的方法，其中使用外部酸扩散工艺来从半导体衬底的一个器件区域选择性地去除一部分阈值电压调节层。 外部酸扩散方法使用酸性聚合物，其在烘烤时表现出酸浓度的增加，其可以扩散到阈值电压调节层的下部暴露部分。 扩散的酸与阈值电压调节层的暴露部分反应，提供酸反应层，与不暴露于扩散的酸的阈值电压调节层的横向相邻部分相比，可以选择性地除去酸反应层。
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公开(公告)号：US20120171818A1
公开(公告)日：2012-07-05
申请号：US13418716
申请日：2012-03-13
IPC分类号： H01L21/50
CPC分类号： H01L23/5389 , H01L21/76898 , H01L24/80 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2924/12044
摘要： Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.
摘要翻译： 第一基板和第二基板中的每一个包括具有耐扩散电介质材料如氮化硅的表面。 凹陷区域形成在耐扩散电介质材料中，并且填充有可粘结介电材料。 第一和第二基板中的金属焊盘和可接合的介质材料部分的图案可以具有镜面对称性。 第一和第二基板通过金属焊盘和可接合的介电材料部分之间的触点之间的触点进行物理接触和接合。 通过基底通孔（TSV）结构通过键合介电材料部分形成。 位于TSV结构周围的每对键合的电介质材料部分之间的界面由两个扩散电阻的介电材料层封装，使得接合界面处的金属的扩散被包含在每对键合介电材料部分内。
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公开(公告)号：US20110101537A1
公开(公告)日：2011-05-05
申请号：US12608368
申请日：2009-10-29
IPC分类号： H01L23/538 , H01L21/768 , H01L21/50
CPC分类号： H01L23/5389 , H01L21/76898 , H01L24/80 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2924/12044
摘要： Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.
摘要翻译： 第一基板和第二基板中的每一个包括具有耐扩散电介质材料如氮化硅的表面。 凹陷区域形成在耐扩散电介质材料中，并且填充有可粘结介电材料。 第一和第二基板中的金属焊盘和可接合的介质材料部分的图案可以具有镜面对称性。 第一和第二基板通过金属焊盘和可接合的介电材料部分之间的触点之间的触点进行物理接触和接合。 通过基底通孔（TSV）结构通过键合介电材料部分形成。 位于TSV结构周围的每对键合的电介质材料部分之间的界面由两个扩散电阻的介电材料层封装，使得接合界面处的金属的扩散被包含在每对键合介电材料部分内。
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8.发明申请METHOD AND STRUCTURE FOR GATE HEIGHT SCALING WITH HIGH-K/METAL GATE TECHNOLOGY 有权采用高K /金属门技术进行门高度测量的方法与结构公开(公告)号：US20100237435A1
公开(公告)日：2010-09-23
申请号：US12715781
申请日：2010-03-02
CPC分类号： H01L21/823437 , H01L21/28088 , H01L27/0629 , H01L27/0802 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.
摘要翻译： 一种在高k /金属栅极晶体管中缩放金属栅极高度的方法和结构。 一种方法包括形成伪栅极和至少一个多晶硅特征，所述多晶硅特征全部由相同的多晶硅层形成，并且其中所述伪栅极形成在与晶体管相关联的栅极金属层上。 该方法还包括选择性地去除伪栅极，同时保护至少一个多晶硅特征。 该方法还包括在栅极金属层上形成栅极接触，从而形成高度小于至少一个多晶硅特征的一半高度的金属栅极。
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公开(公告)号：US07608489B2
公开(公告)日：2009-10-27
申请号：US11380689
申请日：2006-04-28
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译： 本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。 在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。
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10.发明申请公开(公告)号：US20080224218A1
公开(公告)日：2008-09-18
申请号：US11685458
申请日：2007-03-13
申请人： Yaocheng Liu , Ricardo A. Donaton , Kern Rim
发明人： Yaocheng Liu , Ricardo A. Donaton , Kern Rim
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66545 , H01L29/66636
摘要： A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.
摘要翻译： CMOS结构包括包括n-FET沟道区的n-FET器件和包括p-FET沟道区的p-FET器件。 n-FET沟道区包括位于硅 - 锗合金材料层上的第一硅材料层。 p-FET沟道包括位于硅 - 锗 - 碳合金材料层上的第二硅材料层。 硅 - 锗合金材料层在n-FET通道内引起所需的拉伸应变。 硅 - 锗 - 合金材料层抑制了p-FET沟道区内的不希望的拉伸应变。 可以通过选择性地将碳包含在形成硅 - 锗合金材料层的硅 - 锗合金材料中来形成由硅 - 锗 - 碳合金材料层构成的硅 - 锗 - 碳合金材料。
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