公开(公告)号：US08358889B2

公开(公告)日：2013-01-22

申请号：US12787652

申请日：2010-05-26

申请人： Radu Barsan ,  Lew Stolpner

发明人： Radu Barsan ,  Lew Stolpner

IPC分类号： G02B6/34

CPC分类号： G02B6/124 ,  B82Y20/00 ,  G02B6/12007 ,  G02B6/1225 ,  G02B6/132 ,  G02B6/134

摘要： The present invention relates to various methods of fabricating Planar Bragg Gratings (PBG) in a doped waveguide in a Planar Lightwave Circuit (PLC) device, suppressing unwanted parasitic grating effects during fabrication of the device. One approach to reduce parasitic gratings is to use a hard mask before the waveguide photolithography and etch, that results in a steeper sidewall angle that reduces or eliminates the parasitic grating effect. Another method of reducing parasitic grating effect is to deposit a layer of developable Bottom Anti Reflective Coating (BARC) prior to depositing the photo resist for waveguide etch. A third method of resisting parasitic gratings comprises using a planarizing undoped silica layer as a barrier layer on top of the core. During subsequent high temperature annealing germanium outdiffuses laterally into the cladding. The net effect is an optical waveguide with improved lateral uniformity because germanium diffusion smoothes out the sidewall roughness created during the waveguide reactive ion etch process. The undoped silica (SiO2) layer on top of the grating also serves the purpose of significantly reducing germanium outdiffusion from the core in the upward direction.

摘要翻译： 本发明涉及在平面光波电路（PLC）器件中的掺杂波导中制造平面布拉格光栅（PBG）的各种方法，其在器件制造期间抑制不期望的寄生光栅效应。 减少寄生光栅的一种方法是在波导光刻和蚀刻之前使用硬掩模，这导致更陡峭的侧壁角度，其减小或消除寄生光栅效应。 减少寄生光栅效应的另一种方法是在淀积用于波导蚀刻的光致抗蚀剂之前沉积一层可显影的底部防反射涂层（BARC）。 抵抗寄生光栅的第三种方法包括使用平坦化未掺杂的二氧化硅层作为核心顶部上的阻挡层。 在随后的高温退火中锗向外扩散到包层中。 净效应是具有改进的横向均匀性的光波导，因为锗扩散平滑了在波导反应离子蚀刻工艺期间产生的侧壁粗糙度。 光栅顶部的未掺杂的二氧化硅（SiO 2）层也用于在向上的方向上显着地减少核的锗扩散。

公开(公告)号：US06211022B1

公开(公告)日：2001-04-03

申请号：US09241265

申请日：1999-02-01

申请人： Jonathan Lin ,  Radu Barsan ,  Sunil Mehta

发明人： Jonathan Lin ,  Radu Barsan ,  Sunil Mehta

IPC分类号： H01L21336

CPC分类号： H01L21/823481 ,  H01L21/3185 ,  H01L21/76202 ,  H01L21/823418

摘要： A nitride layer is deposited over a field oxide layer used to separate transistors formed in a substrate, the nitride layer serving to decrease transistor current leakage. The nitride layer has a dense lattice, effectively blocking H+ and Na+ penetration from overlying layers into the field oxide. Positive ions such as H+ and Na+ penetrating into the field oxide layer cause a p-substrate under the field oxide layer to become inverted or act like an n-type substrate, creating leakage current between source and drain regions of transistors which the field oxide layer separates. When high transistor threshold voltages such as 12 volts or more are desired, the nitride layer provides a significant reduction in current leakage.

摘要翻译： 氮化物层沉积在用于分离形成在衬底中的晶体管的场氧化物层上，氮化物层用于减小晶体管电流泄漏。 氮化物层具有致密的晶格，有效地阻止H +和Na +从上覆层渗透到场氧化物中。 渗透到场氧化物层中的正离子如H +和Na +导致场氧化物层下的p衬底变为反相或类似于n型衬底，在晶体管的源极和漏极区域之间产生漏电流，其中场氧化物层 分开。 当需要诸如12伏特或更高的高晶体管阈值电压时，氮化物层显着降低电流泄漏。

公开(公告)号：US5854114A

公开(公告)日：1998-12-29

申请号：US947888

申请日：1997-10-09

申请人： Xiao-Yu Li ,  Radu Barsan ,  Sunil D. Mehta

发明人： Xiao-Yu Li ,  Radu Barsan ,  Sunil D. Mehta

IPC分类号： H01L21/762 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11517 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11526

摘要： A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

公开(公告)号：US5841701A

公开(公告)日：1998-11-24

申请号：US785096

申请日：1997-01-21

申请人： Xiao-Yu Li ,  Radu Barsan ,  Sunil Mehta

发明人： Xiao-Yu Li ,  Radu Barsan ,  Sunil Mehta

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C11/34

CPC分类号： G11C16/12 ,  G11C16/10

摘要： A method for improving the endurance and reliability of a floating gate transistor often used in memory applications by controlling the electric field induced across the tunnel oxide region of the floating gate when discharging electrons from the floating gate. The method comprises the steps of: allowing the active region to ground; and applying a program voltage to the floating gate over a period of time and at a magnitude, by increasing the voltage from zero volts to the magnitude over a first period of at least 1 millisecond (ms.), maintaining the voltage at the magnitude for a second period of around 10 ms.-100 ms. sufficient to place charge on the floating gate, and decreasing the voltage from the magnitude during a third period to zero volts in not greater than 50 microseconds.

摘要翻译： 常用于存储器应用中的浮栅晶体管的耐久性和可靠性通过控制在浮置栅极放电电子时跨越浮栅的隧道氧化物区域感应的电场的方法。 该方法包括以下步骤：允许有源区域接地; 并且通过在至少1毫秒（ms）的第一周期上将电压从零伏特增加到幅度，在一段时间和幅度上将编程电压施加到浮动栅极，将电压保持在大小为 大约10 ms.-100 ms的第二个周期。 足以在浮动栅极上放置电荷，并将电压从第三周期内的幅度降低到零伏特以不大于50微秒。

公开(公告)号：US5830795A

公开(公告)日：1998-11-03

申请号：US664190

申请日：1996-06-10

申请人： Sunil D. Mehta ,  Radu Barsan

发明人： Sunil D. Mehta ,  Radu Barsan

IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L21/8234

CPC分类号： H01L27/11521 ,  H01L21/823807 ,  H01L27/0922 ,  H01L27/11558

摘要： A process for forming CMOS transistors on a semiconductor substrate, wherein the plurality of transistors includes high-voltage N-channel and high-voltage P-channel transistors, and low-voltage N-channel and low-voltage P-channel transistors, wherein a tunnel oxide of a first thickness is required and a gate oxide of a second thickness is required is provided. The process comprises the steps of: forming a thick gate oxide on the surface of the substrate; forming a low voltage n-channel transistor mask, the mask including a plurality of windows exposing first portions of the thick gate oxide; implanting an n-type dopant into the substrate through said windows and through the thick gate oxide layer to form an n-dopant implant region; etching a first portion of the thick gate oxide exposing the surface of the substrate overlying the n-dopant implant region; stripping the low voltage n-channel mask; forming a low voltage p-channel transistor mask, the mask including a plurality of windows exposing the second portions of the thick gate oxide; implanting a p-type dopant into the substrate through said windows and through the thick gate oxide layer; etching a second portion of the thick gate oxide layer thereby exposing a first and second portions of the substrate surface; and simultaneously forming a tunnel oxide on the first exposed portion of the substrate and gate oxide on the second exposed portion of the substrate.

摘要翻译： 一种用于在半导体衬底上形成CMOS晶体管的工艺，其中所述多个晶体管包括高压N沟道和高压P沟道晶体管，以及低电压N沟道和低电压P沟道晶体管，其中a 需要第一厚度的隧道氧化物，并且需要第二厚度的栅极氧化物。 该方法包括以下步骤：在衬底的表面上形成厚栅极氧化物; 形成低电压n沟道晶体管掩模，所述掩模包括暴露所述厚栅极氧化物的第一部分的多个窗口; 通过所述窗口和通过厚栅氧化层将n型掺杂剂注入到衬底中以形成n掺杂剂注入区域; 蚀刻暴露覆盖在n-掺杂剂注入区域上的衬底的表面的厚栅极氧化物的第一部分; 剥离低电压n沟道掩模; 形成低电压p沟道晶体管掩模，所述掩模包括暴露所述厚栅极氧化物的第二部分的多个窗口; 通过所述窗口和通过厚栅极氧化物层将p型掺杂剂注入衬底; 蚀刻厚栅极氧化物层的第二部分，从而暴露衬底表面的第一和第二部分; 并且同时在衬底的第一暴露部分和衬底的第二暴露部分上的栅极氧化物上形成隧道氧化物。

公开(公告)号：US20100303411A1

公开(公告)日：2010-12-02

申请号：US12787652

申请日：2010-05-26

申请人： Radu Barsan ,  Lew Stolpner

发明人： Radu Barsan ,  Lew Stolpner

IPC分类号： G02B6/34 ,  G02B6/10

CPC分类号： G02B6/124 ,  B82Y20/00 ,  G02B6/12007 ,  G02B6/1225 ,  G02B6/132 ,  G02B6/134

摘要： The present invention relates to various methods of fabricating Planar Bragg Gratings (PBG) in a doped waveguide in a Planar Lightwave Circuit (PLC) device, suppressing unwanted parasitic grating effects during fabrication of the device. One approach to reduce parasitic gratings is to use a hard mask before the waveguide photolithography and etch, that results in a steeper sidewall angle that reduces or eliminates the parasitic grating effect. Another method of reducing parasitic grating effect is to deposit a layer of developable Bottom Anti Reflective Coating (BARC) prior to depositing the photo resist for waveguide etch. A third method of resisting parasitic gratings comprises using a planarizing undoped silica layer as a barrier layer on top of the core. During subsequent high temperature annealing germanium outdiffuses laterally into the cladding. The net effect is an optical waveguide with improved lateral uniformity because germanium diffusion smoothes out the sidewall roughness created during the waveguide reactive ion etch process. The undoped silica (SiO2) layer on top of the grating also serves the purpose of significantly reducing germanium outdiffusion from the core in the upward direction.

摘要翻译： 本发明涉及在平面光波电路（PLC）器件中的掺杂波导中制造平面布拉格光栅（PBG）的各种方法，其在器件制造期间抑制不期望的寄生光栅效应。 减少寄生光栅的一种方法是在波导光刻和蚀刻之前使用硬掩模，这导致更陡峭的侧壁角度，其减小或消除寄生光栅效应。 减少寄生光栅效应的另一种方法是在淀积用于波导蚀刻的光致抗蚀剂之前沉积一层可显影的底部防反射涂层（BARC）。 抵抗寄生光栅的第三种方法包括使用平坦化未掺杂的二氧化硅层作为核心顶部上的阻挡层。 在随后的高温退火中锗向外扩散到包层中。 净效应是具有改进的横向均匀性的光波导，因为锗扩散平滑了在波导反应离子蚀刻工艺期间产生的侧壁粗糙度。 光栅顶部的未掺杂的二氧化硅（SiO 2）层也用于在向上的方向上显着地减少核的锗扩散。

公开(公告)号：US5700698A

公开(公告)日：1997-12-23

申请号：US500295

申请日：1995-07-10

申请人： Radu Barsan ,  Jonathan Lin

发明人： Radu Barsan ,  Jonathan Lin

IPC分类号： G01R31/30 ,  G11C29/50 ,  H01L21/8247 ,  H01L27/118 ,  H01L21/8217 ,  H01L21/66

CPC分类号： H01L27/11517 ,  G01R31/30 ,  G11C29/50 ,  G11C29/50016 ,  H01L27/118 ,  G11C16/04 ,  G11C2029/5004

摘要： An improved method for screening a non-volatile memory device or programmable logic device including the steps of initially programming and then erasing a device for a predetermined number of cycles thereby providing a stressed device. Next, the stressed device is erased, providing an erased device. A first voltage value is measured across the floating gate of each cell of the erased device which is then stored for a predetermined period of time at a first predetermined temperature, providing a stored device. Next, the stored device is baked at a second predetermined temperature resulting in a baked device. Then, a second voltage value is measured across the floating gate of each cell of the baked device. Each of the first and the second voltage values are subtracted to provide a plurality of measured voltage drop values each of which are compared to an acceptable predetermined voltage drop value. The baked device is identified as defective and is discarded if any of the measured voltage drop values are greater than the acceptable predetermined voltage drop value. The first predetermined temperature is room temperature (i.e., 0.degree.-50.degree. C.), and the second predetermined temperature is greater than or equal to 250.degree. C.

摘要翻译： 一种用于筛选非易失性存储器件或可编程逻辑器件的改进方法，包括以下步骤：首先对预定数量的循环进行编程，然后擦除器件，从而提供受压器件。 接下来，应力装置被擦除，提供一个已擦除的装置。 在擦除装置的每个单元的浮动栅极上测量第一电压值，然后在第一预定温度下存储预定时间段，从而提供存储的装置。 接下来，将所存储的装置以第二预定温度进行烘烤，得到烘烤装置。 然后，在烘烤设备的每个单元的浮动栅极上测量第二电压值。 减去第一和第二电压值中的每一个以提供多个测量的电压降值，每个电压降与可接受的预定电压降值进行比较。 被烘烤的装置被识别为有缺陷的，并且如果测量的电压降值中的任一个大于可接受的预定电压降值，则将其丢弃。 第一预定温度为室温（即0℃-50℃），第二预定温度为大于或等于250℃。

公开(公告)号：US06071784A

公开(公告)日：2000-06-06

申请号：US921003

申请日：1997-08-29

申请人： Sunil D. Mehta ,  Radu Barsan

发明人： Sunil D. Mehta ,  Radu Barsan

IPC分类号： H01L21/768 ,  H01L21/336

CPC分类号： H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895

摘要： This invention includes a semiconductor device having a gate formed on a semiconductor substrate with a low hydrogen content etch stop or barrier layer formed over the gate, and methods for manufacturing a semiconductor device with an etch stop or barrier layer with low free hydrogen content. The semiconductor device may have a hydrogen getter layer formed between the gate and the etch stop or barrier layer. The etch stop or barrier layer is a high temperature PECVD nitride film, a high temperature PECVD oxynitride film or a high temperature LPCVD nitride film. The hydrogen getter layer is P-doped film having a thickness between about 500 .ANG. and about 2000 .ANG. and is a PSG, BPSG, PTEOS deposited oxide film, or a BPTEOS deposited oxide film. The low free hydrogen content of the etch stop layer or barrier layer is achieved by a high temperature annealing step, performed at a higher temperature than the deposition temperature of the etch stop or barrier layer. Specific uses of the etch stop or barrier layers include manufacture of electrical contacts and local interconnects.

摘要翻译： 本发明包括半导体器件，其具有形成在半导体衬底上的栅极，该栅极形成在栅极上形成的低氢含量蚀刻阻挡层或阻挡层，以及用于制造具有低自由氢含量的蚀刻停止层或阻挡层的半导体器件的方法。 半导体器件可以具有形成在栅极和蚀刻停止层或阻挡层之间的吸氢剂层。 蚀刻停止层或阻挡层是高温PECVD氮化物膜，高温PECVD氮氧化物膜或高温LPCVD氮化物膜。 吸氢剂层是厚度在约500至约2000之间的P掺杂膜，是PSG，BPSG，PTEOS沉积氧化物膜或BPTEOS沉积氧化物膜。 通过高温退火步骤实现蚀刻停止层或阻挡层的低自由氢含量，其在比蚀刻停止层或阻挡层的沉积温度更高的温度下进行。 蚀刻停止层或阻挡层的具体用途包括制造电触点和局部互连。

公开(公告)号：US6064105A

公开(公告)日：2000-05-16

申请号：US134174

申请日：1998-08-14

申请人： Xiao-Yu Li ,  Radu Barsan ,  Sunil D. Mehta

发明人： Xiao-Yu Li ,  Radu Barsan ,  Sunil D. Mehta

IPC分类号： H01L21/762 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L21/8244

CPC分类号： H01L27/11517 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11526

摘要： A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

摘要翻译： 提供浅沟槽隔离结构及其与非易失性存储器件一起使用的形成方法，以便保持足够的数据保留。 在半导体衬底的顶表面上形成外延层。 在外延层的顶表面上形成阻挡氧化层。 氮化物层沉积在阻挡氧化物层的顶表面上。 沟槽通过外延层和阻挡氧化物层形成在外延层表面下方大于4000的深度，以便产生隔离区，以便电隔离外延层中的有源区。 衬垫氧化物形成在沟槽的侧壁和底部上，厚度在750至1500之间。 结果，由于随后的制造工艺步骤，衬垫氧化物层的薄度变小，可以防止侧壁中的漏电流。

公开(公告)号：US5908308A

公开(公告)日：1999-06-01

申请号：US980883

申请日：1997-11-26

申请人： Radu Barsan ,  Jonathan Lin ,  Sunil Mehta

发明人： Radu Barsan ,  Jonathan Lin ,  Sunil Mehta

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H11L21/8238 ,  H01L21/31 ,  H01L21/336 ,  H01L21/469 ,  H01L21/76

CPC分类号： H01L21/02129 ,  H01L21/31625 ,  H01L21/76202 ,  H01L21/76834 ,  H01L21/823475

摘要： Controlling the thickness of borophosphorous tetraethyl orthosilicate (BPTEOS) used as all or part of the first inter-layer dielectric (ILD0) in manufacturing a semiconductor device containing an array of transistors to control the field leakage between transistors. Reducing field leakage enables the thickness of field oxide, typically used to reduce field leakage, to be reduced to increase device density in the transistor array.

摘要翻译： 控制在制造包含晶体管阵列以控制晶体管之间的场漏电的半导体器件中用作全部或部分第一层间电介质（ILD0）的硼磷酸四乙基原硅酸盐（BPTEOS）的厚度。 减小场漏电流使得通常用于减少场漏电的场氧化物的厚度减小以增加晶体管阵列中的器件密度。