Specifying an access hint for prefetching limited use data in a cache hierarchy
    3.
    发明授权
    Specifying an access hint for prefetching limited use data in a cache hierarchy 失效
    指定在缓存层次结构中预取有限使用数据的访问提示

    公开(公告)号:US08176254B2

    公开(公告)日:2012-05-08

    申请号:US12424681

    申请日:2009-04-16

    IPC分类号: G06F13/00

    摘要: A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the processing unit that a program executing on the data processing system may soon access a cache block addressed within the DCBT instruction. The access hint is contained in a code point stored in a subfield of the DCBT instruction. In response to detecting that the code point is set to a specific value, the data addressed in the DCBT instruction is prefetched into an entry in the lower level cache. The entry may then be updated as a least recently used entry of a plurality of entries in the lower level cache. In response to a new cache block being fetched to the cache, the prefetched cache block is cast out of the cache.

    摘要翻译: 一种用于指定预取有限使用数据的访问提示的系统和方法。 处理单元接收具有指示给处理单元的访问提示的数据高速缓存块触摸(DCBT)指令,即在数据处理系统上执行的程序可以很快访问在DCBT指令内寻址的高速缓存块。 访问提示包含在存储在DCBT指令的子字段中的代码点中。 响应于检测到代码点被设置为特定值,DCBT指令中寻址的数据被预取到低级缓存中的条目中。 然后可以将条目作为较低级别高速缓存中的多个条目的最近最少使用的条目来更新。 响应于将新的高速缓存块提取到高速缓存,预取的高速缓存块被抛出高速缓存。

    USE OF HARDWARE TO MANAGE DEPENDENCIES BETWEEN GROUPS OF NETWORK DATA PACKETS
    5.
    发明申请
    USE OF HARDWARE TO MANAGE DEPENDENCIES BETWEEN GROUPS OF NETWORK DATA PACKETS 有权
    使用硬件管理网络数据包组合之间的依赖关系

    公开(公告)号:US20100179989A1

    公开(公告)日:2010-07-15

    申请号:US12727526

    申请日:2010-03-19

    IPC分类号: G06F15/16

    CPC分类号: G06F13/1621

    摘要: A task obtained by a communications processor is decomposed into one or more requests that form a request group. The requests of the request group are sent to main memory and responses to those requests are expected. There may be requests for a plurality of request groups being processed concurrently. However, responses to the request groups are to be returned to the communications processor in the order in which the request groups were sent from the communications processor. To ensure this ordering, dependencies between the request groups are tracked by hardware coupled to the communications processor.

    摘要翻译: 由通信处理器获得的任务被分解成形成请求组的一个或多个请求。 请求组的请求被发送到主存储器,并且期望对这些请求的响应。 可能需要同时处理多个请求组的请求。 但是,请求组的响应将按照从通信处理器发送请求组的顺序返回给通信处理器。 为了确保这种排序,请求组之间的依赖关系由耦合到通信处理器的硬件进行跟踪。

    USE OF HARDWARE TO MANAGE DEPENDENCIES BETWEEN GROUPS OF NETWORK DATA PACKETS
    6.
    发明申请
    USE OF HARDWARE TO MANAGE DEPENDENCIES BETWEEN GROUPS OF NETWORK DATA PACKETS 失效
    使用硬件管理网络数据包组合之间的依赖关系

    公开(公告)号:US20080256180A1

    公开(公告)日:2008-10-16

    申请号:US12142128

    申请日:2008-06-19

    IPC分类号: G06F15/16

    CPC分类号: G06F13/1621

    摘要: A task obtained by a communications processor is decomposed into one or more requests that form a request group. The requests of the request group are sent to main memory and responses to those requests are expected. There may be requests for a plurality of request groups being processed concurrently. However, responses to the request groups are to be returned to the communications processor in the order in which the request groups were sent from the communications processor. To ensure this ordering, dependencies between the request groups are tracked by hardware coupled to the communications processor.

    摘要翻译: 由通信处理器获得的任务被分解成形成请求组的一个或多个请求。 请求组的请求被发送到主存储器,并且期望对这些请求的响应。 可能需要同时处理多个请求组的请求。 但是,请求组的响应将按照从通信处理器发送请求组的顺序返回给通信处理器。 为了确保这种排序,请求组之间的依赖关系由耦合到通信处理器的硬件进行跟踪。

    Memory bus address snooper logic for determining memory activity without
performing memory accesses
    7.
    发明授权
    Memory bus address snooper logic for determining memory activity without performing memory accesses 失效
    用于在不执行存储器访问的情况下确定存储器活动的存储器总线地址窥探逻辑

    公开(公告)号:US5901326A

    公开(公告)日:1999-05-04

    申请号:US756447

    申请日:1996-11-26

    CPC分类号: G06F13/4243

    摘要: A parallel multiprocessor data processing system having a plurality of nodes for processing data and a switch connected to each of said nodes for switching messages between the nodes, each node having a node processor for defining messages under program control to be sent to another node. Each of the nodes has an I/O processor for controlling the sending of messages to another node via the switch, and a shared memory which can be accessed by both the node processor and the I/O processor. Instructions for the messages to be sent by the I/O processor are stored in mailboxes in the shared memory by the node processor. A comparing circuit compares addresses on the bus to the contents of a plurality of address registers and sets the corresponding bit in a results register for each match. The adapter processor reads the contents of the results register such that the adapter processor may, with a single bus access, determine all mailboxes that have been accessed by the node processor.

    摘要翻译: 一种并行多处理器数据处理系统,具有用于处理数据的多个节点和连接到每个所述节点的交换机,用于在节点之间切换消息,每个节点具有用于定义程序控制下的消息以发送到另一个节点的节点处理器。 每个节点具有用于控制经由交换机将消息发送到另一个节点的I / O处理器,以及可由节点处理器和I / O处理器访问的共享存储器。 由I / O处理器发送的消息的说明由节点处理器存储在共享存储器中的邮箱中。 比较电路将总线上的地址与多个地址寄存器的内容进行比较,并为每个匹配设置结果寄存器中的相应位。 适配器处理器读取结果寄存器的内容,使得适配器处理器可以通过单个总线访问来确定节点处理器已经访问的所有邮箱。