公开(公告)号：US08707016B2

公开(公告)日：2014-04-22

申请号：US12024211

申请日：2008-02-01

Applicant: Ravi K. Arimilli ,  Juan C. Rubio ,  Balaram Sinharoy

Inventor： Ravi K. Arimilli ,  Juan C. Rubio ,  Balaram Sinharoy

IPC: G06F9/30

CPC classification number: G06F9/4843 ,  G06F9/3851

Abstract: A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. The set of helper thread binaries and the set of main thread binaries are partitioned according to common instruction boundaries. As a first partition in the set of main thread binaries executes within a first core, a second partition in the set of helper thread binaries executes within a second core, thus “warming up” the cache in the second core. When the first partition of the main completes execution, a second partition of the main core moves to the second core, and executes using the warmed up cache in the second core.

Abstract translation: 创建一组辅助线程二进制文件来检索一组主线程二进制文件使用的数据。 辅助线程二进制文件集和主线程二进制文件集合根据公共指令边界进行分区。 作为主线程二进制文件集合中的第一分区在第一核心内执行，该辅助线程二进制文件集中的第二分区在第二核心内执行，从而“预热”第二核心中的高速缓存。 当主要的第一分区完成执行时，主核心的第二分区移动到第二核心，并使用第二核心中的预热高速缓存执行。

公开(公告)号：US08612730B2

公开(公告)日：2013-12-17

申请号：US12796124

申请日：2010-06-08

Applicant: Ronald P. Hall ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Balaram Sinharoy ,  Zhong Liang Wang

Inventor： Ronald P. Hall ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Balaram Sinharoy ,  Zhong Liang Wang

IPC: G06F9/00

CPC classification number: G06F9/3851 ,  G06F9/3009 ,  G06F9/327 ,  G06F11/3466 ,  G06F2201/865 ,  G06F2201/88

Abstract: A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.

Abstract translation: 一种用于管理程序中的指令的运行的方法和数据处理系统。 数据处理系统的处理器接收监视单元的监视指令。 处理器确定一组辅助线程的至少一个辅助线程是否可用作辅助线程。 响应于确定所述一组次要线程的至少一个辅助线程可用作辅助线程，所述处理器从所述辅助线程组中选择所述至少一个辅助线程以成为所述辅助线程。 处理器将程序中指令的运行情况从主线程更改为辅助线程。

公开(公告)号：US08387065B2

公开(公告)日：2013-02-26

申请号：US12425343

申请日：2009-04-16

Applicant: Ravi K. Arimilli ,  Ronald N. Kalla ,  Balaram Sinharoy

Inventor： Ravi K. Arimilli ,  Ronald N. Kalla ,  Balaram Sinharoy

IPC: G06F9/46 ,  G06F9/45 ,  G06F9/30 ,  G06F9/40

CPC classification number: G06F9/3001 ,  G06F9/30018 ,  G06F9/3842

Abstract: A method and a data processing system by which population count (popcount) operations are efficiently performed without incurring the latency and loss of critical processing cycles and bandwidth of real time processing. The method comprises: identifying data to be stored to memory for which a popcount may need to be determined; speculatively performing a popcount operation on the data as a background process of the processor while the data is being stored to memory; storing the data to a first memory location; and storing a value of the popcount generated by the popcount operation within a second memory location. The method further comprises: determining a size of data; determining a granular level at which the popcount operation on the data will be performed; and reserving a size of said second memory location that is sufficiently large to hold the value of the popcount.

Abstract translation: 一种方法和数据处理系统，通过该方法和数据处理系统有效地执行人口计数（popcount）操作，而不会导致关键处理周期的延迟和丢失以及实时处理的带宽。 该方法包括：识别要存储到可能需要确定一个弹出窗口的存储器的数据; 在将数据存储到存储器中的情况下，作为处理器的后台处理推测性地对数据进行弹出数据操作; 将数据存储到第一存储器位置; 以及将由所述popcount操作生成的所述popcount的值存储在第二存储器位置内。 该方法还包括：确定数据的大小; 确定将执行对数据的弹出数据操作的粒度级别; 以及保留所述第二存储器位置的大小足够大以保持所述用户名的值。

公开(公告)号：US08359589B2

公开(公告)日：2013-01-22

申请号：US12024191

申请日：2008-02-01

Applicant: Ravi K. Arimilli ,  Juan C. Rubio ,  Balaram Sinharoy

Inventor： Ravi K. Arimilli ,  Juan C. Rubio ,  Balaram Sinharoy

IPC: G06F9/44 ,  G06F9/45 ,  G06F15/167 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F8/41 ,  G06F9/383 ,  G06F9/3851

Abstract: A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. If executing a portion of the set of helper thread binaries results in the retrieval of data needed by the set of main thread binaries, then that retrieved data is utilized by the set of main thread binaries.

Abstract translation: 创建一组辅助线程二进制文件来检索一组主线程二进制文件使用的数据。 如果执行一组辅助线程二进制文件的一部分导致检索主线程二进制文件集所需的数据，那么该检索的数据由主线程二进制文件集合使用。

公开(公告)号：US08285971B2

公开(公告)日：2012-10-09

申请号：US12336315

申请日：2008-12-16

Applicant: Ravi K. Arimilli ,  Balaram Sinharoy

Inventor： Ravi K. Arimilli ,  Balaram Sinharoy

IPC: G06F12/00

CPC classification number: G06F9/383 ,  G06F9/30094 ,  G06F9/345

Abstract: A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation.

Abstract translation: 处理器包括执行指令的至少一个执行单元，耦合到所述至少一个执行单元的至少一个寄存器文件，其缓冲由所述至少一个执行单元访问的操作数，指令排序单元，其通过 所述至少一个执行单元和地址生成加速器。 地址产生加速器响应于从指令排序单元接收的发起信号，计算并输出操作的操作数的第一和第二有效地址。

公开(公告)号：US08266381B2

公开(公告)日：2012-09-11

申请号：US12024170

申请日：2008-02-01

Applicant: Ravi K. Arimilli ,  Gheorghe C. Cascaval ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

Inventor： Ravi K. Arimilli ,  Gheorghe C. Cascaval ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0822 ,  G06F2212/507 ,  G06F2212/6028

Abstract: In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.

Abstract translation: 在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。 响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。 响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。

公开(公告)号：US08140764B2

公开(公告)日：2012-03-20

申请号：US12985726

申请日：2011-01-06

Applicant: Xiaowei Shen ,  Balaram Sinharoy ,  Robert B. Tremaine ,  Robert W. Wisniewski

Inventor： Xiaowei Shen ,  Balaram Sinharoy ,  Robert B. Tremaine ,  Robert W. Wisniewski

IPC: G06F12/00

CPC classification number: G06F12/0864 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

Abstract translation: 提供了一种重新配置高速缓冲存储器的方法。 一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。 分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等 重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

公开(公告)号：US07996564B2

公开(公告)日：2011-08-09

申请号：US12425093

申请日：2009-04-16

Applicant: Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ronald N. Kalla ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William E. Speight ,  William J. Starke

Inventor： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ronald N. Kalla ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William E. Speight ,  William J. Starke

IPC: G06F12/00

CPC classification number: G06F9/54 ,  G06F12/10 ,  G06F12/1081

Abstract: A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.

Abstract translation: 分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器 由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。 在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。 本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问 数据中心为远程存储器的节点ID。

公开(公告)号：US07934061B2

公开(公告)日：2011-04-26

申请号：US12145034

申请日：2008-06-24

Applicant: Dilma Menezes da Silva ,  Elmootazbellah Nabil Elnozahy ,  Orran Yaakov Krieger ,  Hazim Shafi ,  Xiaowei Shen ,  Balaram Sinharoy ,  Robert Brett Tremaine

Inventor： Dilma Menezes da Silva ,  Elmootazbellah Nabil Elnozahy ,  Orran Yaakov Krieger ,  Hazim Shafi ,  Xiaowei Shen ,  Balaram Sinharoy ,  Robert Brett Tremaine

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/00

CPC classification number: G06F12/08 ,  G06F12/0893 ,  G06F2212/251 ,  G06F2212/253

Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

Abstract translation: 考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。 许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。 因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。 几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

公开(公告)号：US07921275B2

公开(公告)日：2011-04-05

申请号：US12024598

申请日：2008-02-01

Applicant: Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Balaram Sinharoy ,  Hanhong Xue

Inventor： Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Balaram Sinharoy ,  Hanhong Xue

IPC: G06F12/00

CPC classification number: G06F12/0862 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/3877

Abstract: While an asynchronous memory move (AMM) operation is ongoing, a prefetch request for data from the source effective address or the destination effective address triggers cache injection by the AMM mover of relevant data from the stream of data being moved in the physical memory. The memory controller forwards the first prefetched line to the prefetch engine and L1 cache, the next cache lines in the sequence of data to the L2 cache, and a subsequent set of cache lines to the L3 cache. The memory controller then forwards the remaining data to the destination memory location. Quick access to prefetch data is enabled by buffering the stream of data in the upper caches rather than placing all the moved data within the memory. Also, the memory controller places moved data into only a subset of the available cache lines of the upper level cache.

Abstract translation: 当异步存储器移动（AMM）操作正在进行时，来自源有效地址或目的地有效地址的数据的预取请求触发AMM移动器对来自物理存储器中移动的数据流的相关数据的高速缓存注入。 存储器控制器将第一预取行转发到预取引擎和L1高速缓存，将数据序列中的下一个高速缓存行转发到L2高速缓存，以及将后续的一组高速缓存行转发到L3高速缓存。 存储器控制器然后将剩余的数据转发到目的地存储器位置。 通过缓存高速缓存中的数据流，而不是将所有移动的数据放在内存中，可以快速访问预取数据。 此外，存储器控制器将移动的数据仅放置在高级缓存的可用高速缓存行的子集中。