公开(公告)号：US4451882A

公开(公告)日：1984-05-29

申请号：US323276

申请日：1981-11-20

Applicant: Valery L. Dshkhunian ,  Eduard E. Ivanov ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Alexei A. Ryzhov ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin

Inventor： Valery L. Dshkhunian ,  Eduard E. Ivanov ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Alexei A. Ryzhov ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin

IPC: G06F9/48 ,  G06F9/18 ,  G06F9/16 ,  G06F15/16

CPC classification number: G06F9/4812

Abstract: A data processing system intended for handling multiple tasks and comprising at least two processors, a memory unit and an I/O unit which are all connected to a data address and control signal transmission line. Each of the processors comprises an arithmetic-logic unit, a scratch pad memory, a processor status register, an interface, and a control unit which are all interconnected by a processor data bus. Each of the processors further contains an address interrupt unit whose input/output is connected to the data address and control signal transmission line. A first output of the address interrupt unit is connected to the processor data bus and its second output is connected to a second input of the control unit. A second control output of the control unit is connected to the input of the address interrupt unit. The invention helps increase the throughput of a data processing system and simplify the programming of interaction between the system's processors.

Abstract translation: 一种用于处理多个任务并且包括至少两个处理器，存储单元和I / O单元的数据处理系统，其全部连接到数据地址和控制信号传输线。 每个处理器包括算术逻辑单元，便携式存储器，处理器状态寄存器，接口和控制单元，它们都由处理器数据总线互连。 每个处理器还包含地址中断单元，其输入/输出连接到数据地址和控制信号传输线。 地址中断单元的第一输出连接到处理器数据总线，其第二输出连接到控制单元的第二输入端。 控制单元的第二控制输出连接到地址中断单元的输入。 本发明有助于提高数据处理系统的吞吐量并简化系统处理器之间的交互编程。

公开(公告)号：US4482950A

公开(公告)日：1984-11-13

申请号：US307942

申请日：1981-09-24

Applicant: Valery L. Dshkhunian ,  Eduard E. Ivanov ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Jury E. Chicherin

Inventor： Valery L. Dshkhunian ,  Eduard E. Ivanov ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Jury E. Chicherin

IPC: G06F13/36 ,  G06F15/167 ,  G06F13/00 ,  G06F9/22

CPC classification number: G06F13/36 ,  G06F15/167

Abstract: A single-chip microcomputer comprises a processor incorporating a computation process control unit and an operation execution unit. The microcomputer further comprises a memory unit, an interface, a buffer storage cell, and a unit to control exchange of information transmitted through a system line. All these units and the processor with its computation process control unit and operation excution unit are interconnected by a bidirectional bus. The processor also includes a buffer storage cell, a processor information exchange control unit, and an address comparator, which are all interconnected. The single-chip microcomputer further contains a bus arbiter and a system line arbiter which are connected to the unit to control exchange of information transmitted through the system line. Finally, the microcomputer includes a system line address comparator connected to the processor and buffer storage cell. The single-chip microcomputer according to the invention can be combined into a system with a common memory field.

Abstract translation: 单片微计算机包括具有计算处理控制单元和操作执行单元的处理器。 微型计算机还包括存储器单元，接口，缓冲存储单元和用于控制通过系统线传输的信息的交换的单元。 所有这些单元和具有其计算过程控制单元和操作排除单元的处理器通过双向总线相互连接。 处理器还包括所有互连的缓冲存储单元，处理器信息交换控制单元和地址比较器。 单片机还包括总线仲裁器和系统线路仲裁器，其连接到单元以控制通过系统线传输的信息的交换。 最后，微型计算机包括连接到处理器和缓冲存储单元的系统线地址比较器。 根据本发明的单片机可以组合成具有公共存储区的系统。

公开(公告)号：US4467413A

公开(公告)日：1984-08-21

申请号：US270526

申请日：1981-06-08

Applicant: Valery L. Dshkhunian ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin

Inventor： Valery L. Dshkhunian ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin

IPC: G06F13/26 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F9/18

CPC classification number: G06F13/26 ,  G06F13/36 ,  G06F13/38 ,  G06F13/4027 ,  G06F13/423

Abstract: Microprocessor apparatus for data exchange is controlled by information supplied via a microinstruction bus and a triggering line and transmits data from some external bidirectional data buses to other such buses. Data is supplied via data exchange units (1.sub.1, 1.sub.2, 2), internal bidirectional data buses and a switch. In addition to the transmission of information, the microprocessor apparatus can, depending on the code of the microinstruction, count the number of transmitted words via a counter and compare or mask data or arbitrate transmitted data via a data processing/converting unit. While executing microinstructions, the counter, the data processing unit, a register unit and a switch shape distinguishing features of the processed information, to be later fed to a conditional operation unit. The conditional operation unit shapes a generalized condition for readjustment of operation of a control unit.

Abstract translation: PCT No.PCT / SU79 / 00117 Sec。 371日期：1981年6月8日 102（e）日期1981年6月8日PCT提交1979年11月28日PCT公布。 第WO81 / 01622号公报 日期：1981年6月11日。用于数据交换的微处理器装置由通过微指令总线和触发线提供的信息控制，并将数据从一些外部双向数据总线传送到其他这样的总线。 数据通过数据交换单元（11,12,2），内部双向数据总线和开关提供。 除了信息传输之外，微处理器装置可以根据微指令的代码经由计数器对发送的字数进行计数，并经由数据处理/转换单元比较或屏蔽数据或仲裁发送的数据。 在执行微指令时，计数器，数据处理单元，寄存器单元和区分处理信息的特征的开关形状，以后被馈送到条件操作单元。 条件操作单元形成用于重新调节控制单元的操作的通用条件。

公开(公告)号：US4471455A

公开(公告)日：1984-09-11

申请号：US345696

申请日：1982-02-04

Applicant: Valery L. Dshkhunian ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Vladislav R. Naumenkov

Inventor： Valery L. Dshkhunian ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Vladislav R. Naumenkov

IPC: G06F7/50 ,  G06F7/503

CPC classification number: G06F7/503 ,  G06F7/50

Abstract: The carry-forming unit comprises a first MOSFET, a second MOSFET, a third MOSFET, a first inverter, a second inverter, an OR-NOT circuit. The input of the first inverter is connected to the input of the first preparatory function. The output of the first inverter and the drain of the first MOSFET are connected to a carry output. The gate of the first MOSFET and the input of the second inverter are connected to the input of second preparatory function. The sources of the first and second MOSFET's and a first input of the NOR-circuit are connected to the carry input of the carry-forming unit. The drain of the second MOSFET is connected to a power supply line while the pulse input of the first inverter and the gate of the second MOSFET are connected to a clock signal line. The source of the third MOSFET is connected to a common bus and its drain--to the source of the first MOSFET. A second input of the OR-NOT circuit is connected to the output of the second inverter and the output--to the gate of the third MOSFET. The present invention helps increase the speed of multi-bit adders, priority and comparator circuits, which results in an increased capacity of computer systems.

Abstract translation: 进位形成单元包括第一MOSFET，第二MOSFET，第三MOSFET，第一反相器，第二反相器，OR-NOT电路。 第一反相器的输入连接到第一预备功能的输入端。 第一反相器的输出和第一MOSFET的漏极连接到进位输出。 第一个MOSFET的栅极和第二个反相器的输入端连接到第二个预备功能的输入端。 第一和第二MOSFET的源极和NOR电路的第一输入端连接到进位形成单元的进位输入端。 第二MOSFET的漏极连接到电源线，而第一反相器的脉冲输入和第二MOSFET的栅极连接到时钟信号线。 第三个MOSFET的源极连接到公共总线，并将其漏极连接到第一个MOSFET的源极。 OR-NOT电路的第二个输入端连接到第二个反相器的输出端并输出到第三个MOSFET的栅极。 本发明有助于提高多比特加法器，优先级和比较器电路的速度，这导致计算机系统的容量增加。

公开(公告)号：US4471428A

公开(公告)日：1984-09-11

申请号：US338886

申请日：1982-01-12

Applicant: Valery L. Dshkhunian ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin

Inventor： Valery L. Dshkhunian ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin

IPC: G06F15/78 ,  G06F9/22

CPC classification number: G06F15/7814

Abstract: A microcomputer processor comprises a scratch-pad storage, an arithmetic-logical unit, an interface unit and a microprogram unit, all interconnected by means of an intraprocessor data bus, and a processor status register. The processor further comprises a constant file, first and second switching elements connected to the arithmetic-logical unit, a register, a source of logic potentials and a decoder. The present invention helps increase the speed of microcomputer processor and expand its functional capabilities.

Abstract translation: 微处理器包括通过处理器内数据总线互连的便笺存储器，算术逻辑单元，接口单元和微程序单元，以及处理器状态寄存器。 处理器还包括连接到算术逻辑单元的恒定文件，第一和第二开关元件，寄存器，逻辑电位源和解码器。 本发明有助于提高微处理器的速度并扩展其功能。

公开(公告)号：US4488264A

公开(公告)日：1984-12-11

申请号：US387049

申请日：1982-06-10

Applicant: Valery L. Dshkhunian ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Vyacheslav V. Telenkov

Inventor： Valery L. Dshkhunian ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Vyacheslav V. Telenkov

IPC: G11C8/16 ,  G11C13/00

CPC classification number: G11C8/16

Abstract: A transistor storage for entering and storing information in and simultaneously reading information from two columns of a matrix of memory cells with different addresses. The transistor storage comprises two multidigit data buses connected to the columns of the memory cell matrix. Each memory cell of the matrix comprises a storage element and two induced channel transistors connected to the storage element and to the multidigit data buses. The multidigit data buses are connected to write circuits and read amplifiers of a first readout direction and second readout direction, which are connected to an input multidigit data bus and an output multidigit data bus. The write circuits are connected to write and read buses. The read amplifiers are connected to the read bus. A multidigit address bus of the transistor storage is connected to address decoders of the first and second matrix columns; these are connected to access control circuits connected to the write and read buses and to the transistors of all the memory cells of a respective matrix column.

Abstract translation: 晶体管存储器，用于在具有不同地址的存储器单元的矩阵的两列中输入和存储信息并同时读取信息。 晶体管存储器包括连接到存储单元矩阵的列的两个多位数据总线。 矩阵的每个存储单元包括存储元件和连接到存储元件和多位数据总线的两个感应沟道晶体管。 多位数据总线连接到写入电路和第一读出方向和第二读出方向的读取放大器，其连接到输入多位数据总线和输出多位数据总线。 写入电路连接到写入和读取总线。 读取放大器连接到读总线。 晶体管存储器的多位地址总线连接到第一和第二矩阵列的地址解码器; 这些连接到连接到写入和读取总线的访问控制电路以及相应矩阵列的所有存储器单元的晶体管。

公开(公告)号：US4124890A

公开(公告)日：1978-11-07

申请号：US808119

申请日：1977-06-20

Applicant: Alexandr A. Vasenkov ,  Valery L. Dshkhunian ,  Pavel R. Mashevich ,  Petr V. Nesterov ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin ,  Davlet I. Juditsky

Inventor： Alexandr A. Vasenkov ,  Valery L. Dshkhunian ,  Pavel R. Mashevich ,  Petr V. Nesterov ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin ,  Davlet I. Juditsky

IPC: G06F9/28 ,  G06F9/16 ,  G06F15/16

CPC classification number: G06F9/28

Abstract: According to the invention, a microprocessor computing system comprises at least one data processing device and at least one group of execution control elements; said group constitutes a control level and includes at least one microprogram control device which is a group of first-order control elements. The data processing device incorporates a microinstruction register for holding microinstruction codes, a microoperation decoder, a general-purpose register unit for holding operands, an arithmetic/logic unit, a temporary result storage register, a result status register, and at least one data exchange unit having a multichannel communication line to provide for data exchange between other sources and destinations. The microprogram control device producing parallel microinstruction codes incorporates at least one input register, a programmable address unit, a microinstruction storage unit, a feedback register, a microinstruction register, and an output driver unit.Each data processing device and each microprogram control device as well, comprise an internal operating cycle generator to generate clock signals of the internal operating cycle, which are used to control data sequencing in the related device, all said internal operating cycle generators being linked through at least one clock signal bus.

Abstract translation: 根据本发明，微处理器计算系统包括至少一个数据处理装置和至少一组执行控制元件; 所述组构成控制级，并且包括至少一个微程序控制装置，其是一组一级控制元件。 数据处理装置包括用于保存微指令代码的微指令寄存器，微操作解码器，用于保存操作数的通用寄存器单元，算术/逻辑单元，临时结果存储寄存器，结果状态寄存器和至少一个数据交换 单元具有多通道通信线路以提供其他源和目的地之间的数据交换。 产生并行微指令代码的微程序控制装置包括至少一个输入寄存器，可编程地址单元，微指令存储单元，反馈寄存器，微指令寄存器和输出驱动器单元。