公开(公告)号：US5568644A

公开(公告)日：1996-10-22

申请号：US435967

申请日：1995-05-05

Applicant: Matthew R. Nelson ,  Thomas E. Saulpaugh

Inventor： Matthew R. Nelson ,  Thomas E. Saulpaugh

IPC: G06F9/48 ,  G06F3/04 ,  G06F9/18

CPC classification number: G06F9/4812

Abstract: Each device is represented by a node in a hierarchical tree, referred to herein as an interrupt source tree (IST). The root and intermediate nodes of the IST represent dispatching or determining points; this removes the need for the device drivers to contain dispatching code; the drivers now only need to contain interrupt handling code specific to the device itself. At these nodes code is executed to determine which branch to take down the IST. The bottom nodes are the leaf nodes; the leaf nodes identify the device interrupt handler. By moving the determination steps performed by the different device drivers to the nodes of the IST, the device drivers are modular and portable. Furthermore, changes to the computer system configuration, which in the prior art would require modification of all device drivers, can be adapted to by modification of the IST.

Abstract translation: 每个设备由分层树中的节点表示，这里称为中断源树（IST）。 IST的根和中间节点表示调度或确定点; 这不需要设备驱动程序来包含调度代码; 现在的驱动程序只需要包含特定于设备本身的中断处理代码。 在这些节点执行代码以确定哪个分支取下IST。 底层节点是叶节点; 叶节点标识设备中断处理程序。 通过将不同设备驱动程序执行的确定步骤移动到IST的节点，设备驱动程序是模块化和便携式的。 此外，现有技术中需要修改所有设备驱动程序的计算机系统配置的改变可以通过修改IST来适应。

公开(公告)号：US4459659A

公开(公告)日：1984-07-10

申请号：US231553

申请日：1981-02-04

Applicant: Dongsung R. Kim

Inventor： Dongsung R. Kim

IPC: G06F9/46 ,  G06F9/26 ,  G06F9/42 ,  G06F9/48 ,  G06F9/18

CPC classification number: G06F9/4426

Abstract: Subroutine control apparatus for providing shared subroutine control for a plurality of executing tasks. Multiple levels of subroutine entry are provided for each task by employing a plurality of selectably accessible stacks, one for each task, along with corresponding pointer registers. These provide storage for a plurality of return addresses as required for each task during task performance. In addition, an updatable significantly faster access register is provided for each task for storing its most recent return address so as to permit return addresses to be rapidly made available when an executing task reaches the end of a subroutine.

Abstract translation: 用于为多个执行任务提供共享子程序控制的子程序控制装置。 通过采用多个可选择可访问的堆栈，每个任务一个以及相应的指针寄存器，为每个任务提供多个级别的子程序条目。 这些在任务执行期间为每个任务所需的多个返回地址提供存储。 此外，为每个任务提供可更新的显着更快的访问寄存器，用于存储其最新的返回地址，以便当执行任务到达子程序的结束时允许返回地址快速可用。

公开(公告)号：US4451882A

公开(公告)日：1984-05-29

申请号：US323276

申请日：1981-11-20

Applicant: Valery L. Dshkhunian ,  Eduard E. Ivanov ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Alexei A. Ryzhov ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin

Inventor： Valery L. Dshkhunian ,  Eduard E. Ivanov ,  Sergei S. Kovalenko ,  Pavel R. Mashevich ,  Alexei A. Ryzhov ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin

IPC: G06F9/48 ,  G06F9/18 ,  G06F9/16 ,  G06F15/16

CPC classification number: G06F9/4812

Abstract: A data processing system intended for handling multiple tasks and comprising at least two processors, a memory unit and an I/O unit which are all connected to a data address and control signal transmission line. Each of the processors comprises an arithmetic-logic unit, a scratch pad memory, a processor status register, an interface, and a control unit which are all interconnected by a processor data bus. Each of the processors further contains an address interrupt unit whose input/output is connected to the data address and control signal transmission line. A first output of the address interrupt unit is connected to the processor data bus and its second output is connected to a second input of the control unit. A second control output of the control unit is connected to the input of the address interrupt unit. The invention helps increase the throughput of a data processing system and simplify the programming of interaction between the system's processors.

Abstract translation: 一种用于处理多个任务并且包括至少两个处理器，存储单元和I / O单元的数据处理系统，其全部连接到数据地址和控制信号传输线。 每个处理器包括算术逻辑单元，便携式存储器，处理器状态寄存器，接口和控制单元，它们都由处理器数据总线互连。 每个处理器还包含地址中断单元，其输入/输出连接到数据地址和控制信号传输线。 地址中断单元的第一输出连接到处理器数据总线，其第二输出连接到控制单元的第二输入端。 控制单元的第二控制输出连接到地址中断单元的输入。 本发明有助于提高数据处理系统的吞吐量并简化系统处理器之间的交互编程。

公开(公告)号：US4439827A

公开(公告)日：1984-03-27

申请号：US335026

申请日：1981-12-28

Applicant: Dean M. Wilkes

Inventor： Dean M. Wilkes

IPC: G06F9/26 ,  G06F9/18

CPC classification number: G06F9/267

Abstract: A dual fetch microsequencer having two single-ported microprogram memories wherein both the sequential and jump address microinstructions of a binary conditional branch can be simultaneously prefetched, one from each memory. The microprogram is assembled so that the sequential and jump addresses of each branch have opposite odd/even polarities. Accordingly, with all odd addresses in one memory and even in the other, the first instruction of both possible paths can always be prefetched simultaneously. When a conditional branch microinstruction is loaded into the execution register, its jump address or a value corresponding to it is transferred to the address register for the appropriate microprogram memory. The address of the microinstruction in the execution register is incremented and transferred to the address register of the other microprogram memory. Prefetch delays are thereby reduced. Also, when a valid conditional jump address is not provided, that microprogram memory may be transparently overlayed during that microcycle.

Abstract translation: 具有两个单端口微程序存储器的双提取微定序器，其中可以同时预取二进制条件分支的顺序和跳转地址微指令，一个来自每个存储器。 组装微程序使得每个分支的顺序和跳转地址具有相反的奇/极性。 因此，在一个存储器中甚至另一个存储器中的所有奇数地址，两个可能的路径的第一指令可以总是被同时预取。 当条件分支微指令被加载到执行寄存器中时，其跳转地址或与其对应的值被传送到用于适当的微程序存储器的地址寄存器。 执行寄存器中的微指令的地址递增并传送到另一个微程序存储器的地址寄存器。 从而减少预取延迟。 另外，当没有提供有效的条件跳转地址时，该微程序存储器可以在该微循环期间被透明地覆盖。

公开(公告)号：US4435765A

公开(公告)日：1984-03-06

申请号：US322717

申请日：1981-11-18

Applicant: Keiichiro Uchida ,  Hiroshi Tamura ,  Tetsuro Okamoto ,  Shigeaki Okutani

Inventor： Keiichiro Uchida ,  Hiroshi Tamura ,  Tetsuro Okamoto ,  Shigeaki Okutani

IPC: G06F15/78 ,  G06F9/18

CPC classification number: G06F15/8076

Abstract: The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.

Abstract translation: 本发明公开了一种数据处理系统，其中在主存储器单元和操作处理单元之间提供由多个元件组成的多个向量寄存器，所需数据从主存储器单元传送到矢量寄存器并保持在其中 ，并且通过顺序访问所述向量寄存器内的元素来执行诸如逻辑操作的各种处理。 本发明还包括多个存储体，其可以被独立地访问并被提供给矢量寄存器。 每个向量寄存器的一系列元素在多个存储体中交错，并且在每个向量寄存器中具有相同编号的元件被布置在同一存储体中。 为每一类处理指定开始访问所述向量寄存器的一系列元素所必需的定时，使得矢量操作处理可以非常有效地进行而不具有操作数冲突。

公开(公告)号：US4435762A

公开(公告)日：1984-03-06

申请号：US241274

申请日：1981-03-06

Applicant: Charles A. Milligan ,  Edwin R. Videki, II ,  Winston F. Yates

Inventor： Charles A. Milligan ,  Edwin R. Videki, II ,  Winston F. Yates

IPC: G06F3/06 ,  G06F5/06 ,  G06F11/00 ,  G06F11/14 ,  G06F13/12 ,  G06F9/18

CPC classification number: G06F11/00 ,  G06F11/1402 ,  G06F13/122

Abstract: A peripheral device subsystem enables its peripheral devices to operate asynchronously with respect to attaches hosts through the use of managed buffers, new multiple data transfer modes, control and error recovery operations. In a preferred first or buffer mode of operation, all data of each record being transferred can be resident in a buffer before transfer to either a host or device. For a host to device write transfer, receipt of such a record by the buffer results in the subsystem signaling to the host a completion of a transfer to an addressed device even though the device has received none or only part of the data. In a second or tape write mode, recording data in a peripheral device, such as a tape recorder, completion of recording is not signaled until after the buffer has transferred the data to the recorder. In the event allocatable buffer space is insufficient to enable operations in the first or second modes, the subsystem automatically switches to a tape synchronous or third mode of data transfer in which data signals are simultaneously transferred between the buffer and the host and peripheral device. A host SYNCHRONIZE command synchronizes buffer operations to host operations. Data to be recorded in a peripheral device and resident in the buffer can be retrieved by a host via a READ BUFFER command. Errors in the subsystem are reported even when delayed after completion of host operations. Additional mode controls are also disclosed.

Abstract translation: 外围设备子系统使其外围设备能够通过使用托管缓冲区，新的多种数据传输模式，控制和错误恢复操作来异步地连接主机。 在优选的第一或缓冲操作模式中，正在传送的每个记录的所有数据可以在传送到主机或设备之前驻留在缓冲器中。 对于主机到设备写入传送，缓冲器接收到这样的记录导致子系统向主机发送完成传送到寻址设备的完成，即使设备已经接收到没有或只有部分数据。 在第二或磁带写入模式中，在诸如磁带录像机之类的外围设备中记录数据，直到缓冲器将数据传送到记录器之后才完成记录。 在可分配缓冲区空间不足以使得在第一或第二模式中的操作的情况下，子系统自动切换到磁带同步或第三模式的数据传输，其中数据信号在缓冲器与主机和外围设备之间同时传输。 主机SYNCHRONIZE命令将缓冲区操作同步到主机操作。 要记录在外围设备中并驻留在缓冲区中的数据可以由主机通过READ BUFFER命令检索。 即使在主机操作完成后延迟，也会报告子系统中的错误。 还公开了附加模式控制。

公开(公告)号：US4177510A

公开(公告)日：1979-12-04

申请号：US528953

申请日：1974-12-02

Applicant: Marc Appell ,  Georges Lepicard ,  Philippe-Hubert de Rivet ,  John J. Bradley ,  Benjamin S. Franklin

Inventor： Marc Appell ,  Georges Lepicard ,  Philippe-Hubert de Rivet ,  John J. Bradley ,  Benjamin S. Franklin

IPC: G06F12/14 ,  G06F13/00 ,  G06F9/18 ,  G06F9/20

CPC classification number: G06F12/1491

Abstract: Computer data and procedure protection by preventing processes from intering with each other or sharing each other's address space in an unauthorized manner is accomplished in hardware/firmware by restricting addressability to a segmented memory and by a ring protection mechanism.To protect information in segments shared by several processes from misuse by one of these processes a ring protection hardware system is utilized. There are four ring classes numbered 0 through 3. Each ring represents a level of system privilege with level 0 (the innermost ring) having the most privilege and level 3 (the outermost ring) the least. Every procedure in the system has a minimum and a maximum execute ring number assigned to it which specifies who may legally call the procedure. Also maximum write and read ring numbers specify the maximum ring numbers for which a write and/or read operation is permitted.Processes use a segmented address during execution wherein segment tables isolate the address space of the various processes in the system. Hardware checks that the address used by a process is part of the address space assigned to the process, and if the address is outside the prescribed address space, an exception occurs. A process cannot refer to data within the address space of another process because the hardware uses the segment table of the referencing process.

Abstract translation: 通过防止过程彼此干扰或以未经授权的方式共享彼此的地址空间的计算机数据和过程保护通过将可寻址性限制到分段存储器和环保护机制来实现在硬件/固件中。 为了保护由多个进程共享的分段中的信息不被这些进程之一的误用，环网保护硬件系统被利用。 有四个戒指级别为0到3.每个戒指表示具有最高权限级别0（最内圈）和级别3（最外层）的系统权限级别。 系统中的每个过程都具有分配给它的最小和最大执行环号，其中指定谁可以合法地调用该过程。 最大写入和读取振铃编号也指定允许写入和/或读取操作的最大振铃数。 进程在执行期间使用分段地址，其中分段表隔离系统中各种进程的地址空间。 硬件检查进程使用的地址是分配给进程的地址空间的一部分，如果地址在规定的地址空间之外，则会发生异常。 进程不能引用另一进程的地址空间内的数据，因为硬件使用引用过程的段表。

公开(公告)号：US4152764A

公开(公告)日：1979-05-01

申请号：US778290

申请日：1977-03-16

Applicant: William D. Connors ,  Dale M. Junod

Inventor： William D. Connors ,  Dale M. Junod

IPC: G06F12/00 ,  G06F9/52 ,  G06F13/18 ,  G06F15/16 ,  G06F15/177 ,  G06F9/18

CPC classification number: G06F13/18

Abstract: The disclosure describes a floating-priority storage access control arrangement for plural processors to a shared main storage in a multi-processing (MP) system. The shared main storage logically couples the main storage units provided with each of the processors into a single expanse of real addresses available to each processor. Exclusive access to the shared storage is given to any processor for as long as that processor can provide a burst of one or more successive storage requests. The burst ends when that processor misses a storage cycle by not providing a locally granted request.The shared storage access is controlled in each processor by means of an MP priority pointer circuit which receives storage requests granted by a local priority circuit in the processor. The MP priority pointer circuits are interconnected between the processors. When a burst ends for one processor, another processor having one or more pending storage requests is given priority and begins its burst during the missed cycle, continuing with highest priority until it completes its burst by not having a locally granted request during a cycle. If no processor makes a request during a storage cycle, and both processors simultaneously make a request during a following cycle, priority for an access burst is given to the processor which last had priority. Thus, priority flip-flops back and forth between the processors as they respectively access main storage in bursts of requests.

Abstract translation: 本公开描述了一种用于多处理器到多处理（MP）系统中的共享主存储器的浮动优先级存储访问控制装置。 共享主存储器将提供有每个处理器的主存储单元逻辑耦合到每个处理器可用的单个实际地址范围。 只要该处理器可以提供一个或多个连续的存储请求的突发，则向任何处理器提供对共享存储器的独占访问。 当处理器通过不提供本地授权的请求而失去存储周期时，突发结束。

公开(公告)号：US4128880A

公开(公告)日：1978-12-05

申请号：US701119

申请日：1976-06-30

Applicant: Seymour R. Cray, Jr.

Inventor： Seymour R. Cray, Jr.

IPC: G06F9/38 ,  G06F15/78 ,  G06F9/18

CPC classification number: G06F15/8084 ,  G06F9/3885

Abstract: Vector processing in a computer is achieved by means of a plurality of vector registers, a plurality of independent fully segmented functional units, and means for controlling the operation of the vector registers. Operations are performed on data from vector register to functional unit and back to vector register with minimal delay, rather than memory to functional unit and return to memory with its attendant much greater start-up delays. Data may be bulk transferred between memory and some vector registers while other vector registers are involved in vector processing with one or more functional units. In vector processing elements of one or more vector registers are successively transmitted as operands to a functional unit at a rate of one per clock period, and results are transmitted from a functional unit to a receiving vector register at the same rate. In a chaining mode of operation, the elements in a result vector register become available for immediate and simultaneous transmission as operands to another functional unit. In this mode, more than one result can be obtained per clock period.

Abstract translation: 通过多个向量寄存器，多个独立的完全分段的功能单元以及用于控制向量寄存器的操作的装置来实现计算机中的向量处理。 对于从向量寄存器到功能单元的数据执行操作，并以最小的延迟返回到向量寄存器，而不是存储到功能单元，并返回到存储器，伴随着更大的启动延迟。 数据可能在存储器和某些矢量寄存器之间进行批量传输，而其他矢量寄存器涉及具有一个或多个功能单元的向量处理。 在一个或多个矢量寄存器的向量处理单元中，以每个时钟周期的速率连续发送作为操作数的功能单元，结果以相同的速率从功能单元发送到接收向量寄存器。 在链接操作模式下，结果向量寄存器中的元素可用于立即和同时传输作为另一个功能单元的操作数。 在这种模式下，每个时钟周期可以获得多于一个的结果。

公开(公告)号：US4121285A

公开(公告)日：1978-10-17

申请号：US783868

申请日：1977-04-01

Applicant: Frank K. Chen

Inventor： Frank K. Chen

IPC: G06F13/20 ,  G06F9/18

CPC classification number: G06F13/20

Abstract: An automatic alternator for a priority circuit comprises one or more flip-flop circuits connected to the channels of the priority circuit by a plurality of AND gate means which are responsive to outputs of the flip-flop circuits and of the priority circuit channels to alternate the servicing of successive simultaneous signals at two or more requesting ports. The flip-flop circuit input is connected to the requesting ports through an AND gate and changes its operating state in response to the presence of two simultaneous signals at the requesting ports and to a cyclically occurring clock input to the flip-flop circuit. When the operating state of the flip-flop circuit is changed to the alternating mode, the signal at the requesting port served by the priority circuit channel during the preceding cycle is blocked from that channel and another request signal appearing simultaneously at the remaining port or ports is applied to the other channel or channels. For a priority circuit having three or more channels, the automatic alternator circuit permits random or "free race" alternating servicing of simultaneous requests or alternatively may provide servicing of those requests in a predetermined sequence in the manner of a commutator.

Abstract translation: 用于优先电路的自动交流发电机包括一个或多个触发电路，其通过多个与门装置连接到优先电路的通道，触发器电路和优先电路通道的输出响应 在两个或更多个请求端口处对连续的同时信号进行服务。 触发器电路输入通过与门连接到请求端口，并且响应于在请求端口处存在两个同时的信号和向触发器电路的循环发生的时钟输入而改变其工作状态。 当触发器电路的操作状态改变为交替模式时，在前一周期期间由优先电路信道服务的请求端口处的信号被阻塞，并且在剩余端口或同一端口同时出现另一个请求信号 应用于其他频道或频道。 对于具有三个或更多个通道的优先电路，自动交流发电机允许对同时请求进行随机或“自由竞争”交替维修，或者可以以换向器的方式以预定顺序提供对这些请求的服务。