Abstract:
A system comprises: a measurement unit adapted to measure a position/orientation of at least one target object based on an image obtained by capturing the at least one target object; a selection unit adapted to select at least one grippable target object based on the position/orientation; a determination unit adapted to determine, as an object to be gripped, a grippable target object in a state with a highest priority from the at least one grippable target object based on priorities set in advance for states including gripping positions/directions; a gripping unit adapted to grip the object to be gripped in the state with the highest priority; and a changing unit adapted to change the state of the gripped object, to a state in which the gripped object is assembled to the other object.
Abstract:
A measurement device includes a pattern light characteristic setting unit configured to set illumination light having a pattern light characteristic to be projected onto a measurement object, a reflected light measurement unit configured to measure reflected light when the measurement object is irradiated with the illumination light on, an image feature extraction unit configured to extract from the measured reflected light an image feature based on a physical characteristic of the measurement object, a feature distribution calculation unit configured to calculate a distribution characteristic for each local region of the image feature, and a pattern light control unit configured to control the pattern light characteristic of the illumination light, which includes a pattern light characteristic for distance measurement and a pattern light characteristic for image feature extraction, based on the calculated distribution characteristic for each local region.
Abstract:
A method for preparing aRNA to be used for gene expression analysis from an RNA sample extracted from a tissue or cell(s) fixed with a fixative includes an amplification step of the RNA sample by reverse transcription and in vitro transcription, the ratio of aminoallyl uridine 5′-triphosphate (AA-UTP) in a nucleotide reagent used in the in vitro transcription is not less than 5 mol % and less than 25 mol % with respect to the total of uridine 5′-triphosphate (UTP) and AA-UTP.
Abstract:
This invention relates to a composition, kit, or DNA chip comprising polynucleotides and antibodies as probes for detecting, determining, or predicting the presence or metastasis of esophageal cancer, and to a method for detecting, determining, or predicting the presence or metastasis of esophageal cancer using the same.
Abstract:
An object of the invention is to provide a casting nozzle in which attachment and deposition of alumina or the like can be prevented while a drift of molten steel can be prevented.The casting nozzle according to the invention is characterized in that the casting nozzle has a molten steel flow hole portion in which “a plurality of independent protrusion portions and/or concave portions” are disposed so that each of the protrusion portions and/or concave portions has a size satisfying the expression (1): H≧2 mm and the expression (2): L>2×H mm [in which “H” shows the maximum height of the protrusion portion or the maximum depth of the concave portion, and “L” shows the maximum length of a base portion of the protrusion portion or concave portion].
Abstract translation:本发明的一个目的是提供一种铸造喷嘴,其中可以防止氧化铝等的附着和沉积,同时可以防止钢水漂移。 根据本发明的铸造喷嘴的特征在于,铸造喷嘴具有:钢水流动孔部,其中设置有“多个独立的突出部和/或凹部”,使得每个突出部和/或凹部 具有满足表达式(1)的尺寸:H≥2mm和表达式(2):L> 2×H mm [其中“H”表示突出部分的最大高度或凹部的最大深度, “L”表示突出部或凹部的基部的最大长度。
Abstract:
Learning is sequentially executed with respect to weak discriminators based on learning data held in a storage device. Upon learning, an evaluation value for the weak discriminator is calculated. It is discriminated, based on a shift of the evaluation value, whether or not the learning is overlearning. If it is discriminated that the learning is overlearning, new learning data is added. Thus, the overlearning is easily detected and the learning is efficiently executed.
Abstract:
A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.
Abstract:
An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits to perform arithmetic processing based on input analog signals, a capacitor to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits, an analog-to-digital (A/D) conversion circuit to convert the charge amount stored in the capacitor to digital data, and a digital arithmetic circuit to calculate a cumulative value based on the converted digital data.
Abstract:
A plurality of signal processing functions are achieved with the same arithmetic processing circuit by controlling wiring arrangements or signal modulation in accordance with a predetermined arrangement control signal that is output based on circuit arrangement information read from a circuit arrangement information storage unit. Hierarchical parallel processing is realized with small-scale circuit configuration. Further, detection of a predetermined feature and integration of the detection results can be efficiently performed.
Abstract:
A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.