公开(公告)号：US20200098887A1

公开(公告)日：2020-03-26

申请号：US16143326

申请日：2018-09-26

申请人： Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Sean MA ,  Seung Hoon SUNG ,  Nazila HARATIPOUR ,  Tahir GHANI ,  Justin WEBER ,  Shriram SHIVARAMAN

发明人： Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Sean MA ,  Seung Hoon SUNG ,  Nazila HARATIPOUR ,  Tahir GHANI ,  Justin WEBER ,  Shriram SHIVARAMAN

IPC分类号： H01L29/51 ,  H01L29/786 ,  H01L29/49 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66

摘要： Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200098875A1

公开(公告)日：2020-03-26

申请号：US16142036

申请日：2018-09-26

申请人： Seung Hoon SUNG ,  Justin WEBER ,  Matthew METZ ,  Arnab SEN GUPTA ,  Abhishek SHARMA ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Charles KUO ,  Nazila HARATIPOUR ,  Shriram SHIVARAMAN ,  Van H. LE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Sean MA

发明人： Seung Hoon SUNG ,  Justin WEBER ,  Matthew METZ ,  Arnab SEN GUPTA ,  Abhishek SHARMA ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Charles KUO ,  Nazila HARATIPOUR ,  Shriram SHIVARAMAN ,  Van H. LE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Sean MA

IPC分类号： H01L29/417 ,  H01L29/08 ,  H01L29/205 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/108 ,  H01L29/267

摘要： Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200098934A1

公开(公告)日：2020-03-26

申请号：US16141016

申请日：2018-09-25

申请人： Shriram SHIVARAMAN ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Seung Hoon SUNG ,  Nazila HARATIPOUR ,  Abhishek SHARMA

发明人： Shriram SHIVARAMAN ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Seung Hoon SUNG ,  Nazila HARATIPOUR ,  Abhishek SHARMA

IPC分类号： H01L29/786 ,  H01L29/51 ,  H01L29/66 ,  H01L21/324 ,  H01L29/78 ,  H01L27/108 ,  H01L27/24

摘要： Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, where the channel layer includes a first region and a second region, and the first region has a first dopant concentration. A gate electrode is above the first region of the channel layer and separated from the channel layer by a gate dielectric layer. A spacer is next to the gate electrode to separate the gate electrode from a drain electrode or a source electrode above the channel layer. The spacer includes a dopant material in contact with the second region of the channel layer, and the second region has a second dopant concentration different from the first dopant concentration in the first region. Other embodiments may be described and/or claimed.

公开(公告)号：US20200098930A1

公开(公告)日：2020-03-26

申请号：US16141408

申请日：2018-09-25

申请人： Van H. LE ,  Tahi GHANI ,  Jack T. KAVALIEROS ,  Gilbert DEWEY ,  Matthew METZ ,  Miriam RESHOTKO ,  Benjamin CHU-KUNG ,  Shriram SHIVARAMAN ,  Abhishek SHARMA ,  NAZILA HARATIPOUR

发明人： Van H. LE ,  Tahi GHANI ,  Jack T. KAVALIEROS ,  Gilbert DEWEY ,  Matthew METZ ,  Miriam RESHOTKO ,  Benjamin CHU-KUNG ,  Shriram SHIVARAMAN ,  Abhishek SHARMA ,  NAZILA HARATIPOUR

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L27/108 ,  H01L27/24

摘要： Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197804A1

公开(公告)日：2023-06-22

申请号：US17556627

申请日：2021-12-20

申请人： Nazila HARATIPOUR ,  Gilbert DEWEY ,  I-Cheng TUNG ,  Nancy ZELICK ,  Chi-Hing CHOI ,  Jitendra Kumar JHA ,  Jack T. KAVALIEROS

发明人： Nazila HARATIPOUR ,  Gilbert DEWEY ,  I-Cheng TUNG ,  Nancy ZELICK ,  Chi-Hing CHOI ,  Jitendra Kumar JHA ,  Jack T. KAVALIEROS

IPC分类号： H01L29/417 ,  H01L29/45

CPC分类号： H01L29/41791 ,  H01L29/45

摘要： Contact over active gate (COAG) structures with trench contact layers, and methods of fabricating contact over active gate (COAG) structures using trench contact layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is adjacent to the gate structure. A conductive trench contact structure is on the epitaxial source or drain structure. The conductive trench contact structure includes a first planar layer on the epitaxial source or drain structure, a second planar layer on the first planar layer, and a conductive fill material on the second planar layer.

公开(公告)号：US20200098931A1

公开(公告)日：2020-03-26

申请号：US16142075

申请日：2018-09-26

申请人： Abhishek SHARMA ,  Nazila HARATIPOUR ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Shriram SHIVARAMAN ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Matthew V. METZ ,  Arnab SEN GUPTA

发明人： Abhishek SHARMA ,  Nazila HARATIPOUR ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Shriram SHIVARAMAN ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Matthew V. METZ ,  Arnab SEN GUPTA

IPC分类号： H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L27/24 ,  H01L27/108

摘要： Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006575A1

公开(公告)日：2020-01-02

申请号：US16024682

申请日：2018-06-29

申请人： Gilbert DEWEY ,  Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Shriram SHIVARAMAN

发明人： Gilbert DEWEY ,  Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Shriram SHIVARAMAN

IPC分类号： H01L29/786 ,  H01L29/66

摘要： Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US20200006572A1

公开(公告)日：2020-01-02

申请号：US16022494

申请日：2018-06-28

申请人： Abhishek A. SHARMA ,  Yih WANG ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Nazila HARATIPOUR ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Gilbert DEWEY ,  Shriram SHIVARAMAN ,  Matthew V. METZ

发明人： Abhishek A. SHARMA ,  Yih WANG ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Nazila HARATIPOUR ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Gilbert DEWEY ,  Shriram SHIVARAMAN ,  Matthew V. METZ

IPC分类号： H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

摘要： Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.