- 专利标题： VERTICAL THIN FILM TRANSISTORS HAVING SELF-ALIGNED CONTACTS
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申请号： US16022494申请日： 2018-06-28
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公开(公告)号： US20200006572A1公开(公告)日： 2020-01-02
- 发明人: Abhishek A. SHARMA , Yih WANG , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI , Nazila HARATIPOUR , Benjamin CHU-KUNG , Seung Hoon SUNG , Gilbert DEWEY , Shriram SHIVARAMAN , Matthew V. METZ
- 申请人： Abhishek A. SHARMA , Yih WANG , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI , Nazila HARATIPOUR , Benjamin CHU-KUNG , Seung Hoon SUNG , Gilbert DEWEY , Shriram SHIVARAMAN , Matthew V. METZ
- 主分类号： H01L29/786
- IPC分类号： H01L29/786 ; H01L29/417 ; H01L29/423 ; H01L29/49 ; H01L29/66
摘要：
Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.
公开/授权文献
- US11296229B2 Vertical thin film transistors having self-aligned contacts 公开/授权日：2022-04-05
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