公开(公告)号：US08698479B2

公开(公告)日：2014-04-15

申请号：US13434856

申请日：2012-03-30

Applicant: Ming-Sheng Tung

Inventor： Ming-Sheng Tung

IPC: G05F3/08 ,  H01L37/00

CPC classification number: G05F3/30

Abstract: A bandgap reference circuit includes a first circuit, a second circuit and a third circuit. The first circuit is for generating a first current and a first voltage according to a first reference voltage. The second circuit is coupled to the first circuit, for generating a second voltage according to the first voltage. The third circuit is coupled to the first circuit and the second circuit, for generating a voltage offset according to the first current, and generating a bandgap reference voltage according to the second voltage and the voltage offset. The first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.

Abstract translation: 带隙基准电路包括第一电路，第二电路和第三电路。 第一电路用于根据第一参考电压产生第一电流和第一电压。 第二电路耦合到第一电路，用于根据第一电压产生第二电压。 第三电路耦合到第一电路和第二电路，用于根据第一电流产生电压偏移，并根据第二电压和电压偏移产生带隙基准电压。 第一电路和第二电路相互补充以抵消由于温度变化引起的带隙参考电压的变化。

公开(公告)号：US20060255388A1

公开(公告)日：2006-11-16

申请号：US11125676

申请日：2005-05-10

Applicant: Yueh-Chuan Lee ,  Ming-Sheng Tung

Inventor： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC: H01L29/772 ,  H01L27/108 ,  H01L21/8242 ,  H01L21/8232

CPC classification number: H01L29/945 ,  H01L27/1087

Abstract: A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.

Abstract translation: 形成沟槽电容器的方法包括：去除衬底的一部分以在衬底内形成沟槽; 在衬底内的掩埋隔离层处形成; 在所述衬底中至少在围绕所述沟槽的下部的区域中在所述沟槽电容器中形成第一电极; 形成沟槽电容器的电介质层; 以及在所述沟槽中形成所述沟槽电容器的第二电极。 掩埋隔离层与沟槽相交并且具有一个或多个间隙，用于在掩埋隔离层之上的第一衬底区域和掩埋隔离层下面的第二衬底区域之间提供身体接触。

公开(公告)号：US20130294178A1

公开(公告)日：2013-11-07

申请号：US13464998

申请日：2012-05-06

Applicant: MING-SHENG TUNG

Inventor： MING-SHENG TUNG

IPC: G11C7/06

CPC classification number: G11C7/12 ,  G11C11/4091 ,  G11C11/4094

Abstract: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.

Abstract translation: 半导体存储器件包括存储单元，感测放大器，预充电电路和控制信号发生器。 预充电电路具有NMOS晶体管和两个PMOS晶体管，并且用于对位线对的位线进行预充电，其中NMOS晶体管由第一控制信号控制，并且两个PMOS晶体管由第二控制信号控制。 控制信号发生器用于产生第一和第二控制信号，其中仅当第二控制信号处于第一逻辑低电平时，第一控制信号处于逻辑高电平，第一控制信号处于逻辑低电平 当第二控制信号处于第二逻辑低电平或第一逻辑高电平，并且第二逻辑低电平高于第一逻辑低电平时。

公开(公告)号：US20130257396A1

公开(公告)日：2013-10-03

申请号：US13434856

申请日：2012-03-30

Applicant: Ming-Sheng Tung

Inventor： Ming-Sheng Tung

IPC: G05F1/10

CPC classification number: G05F3/30

Abstract: A bandgap reference circuit includes a first circuit, a second circuit and a third circuit. The first circuit is for generating a first current and a first voltage according to a first reference voltage. The second circuit is coupled to the first circuit, for generating a second voltage according to the first voltage. The third circuit is coupled to the first circuit and the second circuit, for generating a voltage offset according to the first current, and generating a bandgap reference voltage according to the second voltage and the voltage offset. The first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.

Abstract translation: 带隙基准电路包括第一电路，第二电路和第三电路。 第一电路用于根据第一参考电压产生第一电流和第一电压。 第二电路耦合到第一电路，用于根据第一电压产生第二电压。 第三电路耦合到第一电路和第二电路，用于根据第一电流产生电压偏移，并根据第二电压和电压偏移产生带隙基准电压。 第一电路和第二电路相互补充以抵消由于温度变化引起的带隙参考电压的变化。

公开(公告)号：US07320912B2

公开(公告)日：2008-01-22

申请号：US11125676

申请日：2005-05-10

Applicant: Yueh-Chuan Lee ,  Ming-Sheng Tung

Inventor： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC: H01L21/8242

CPC classification number: H01L29/945 ,  H01L27/1087

Abstract: A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.

Abstract translation: 形成沟槽电容器的方法包括：去除衬底的一部分以在衬底内形成沟槽; 在衬底内的掩埋隔离层处形成; 在所述衬底中至少在围绕所述沟槽的下部的区域中在所述沟槽电容器中形成第一电极; 形成沟槽电容器的电介质层; 以及在所述沟槽中形成所述沟槽电容器的第二电极。 掩埋隔离层与沟槽相交并且具有一个或多个间隙，用于在掩埋隔离层之上的第一衬底区域和掩埋隔离层下面的第二衬底区域之间提供身体接触。

公开(公告)号：US20070090409A1

公开(公告)日：2007-04-26

申请号：US11258119

申请日：2005-10-26

Applicant: Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

Inventor： Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

IPC: H01L29/76 ,  H01L29/745

CPC classification number: H01L27/105 ,  H01L21/823456 ,  H01L27/1052

Abstract: The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. The semiconductor device also comprises a barrier layer, which is located in the memory array area and the periphery circuit area, an undoped oxide barrier, which is located on the barrier layer in the periphery circuit area, and a boron-containing silicate glass, which is located on the barrier layer in the memory array area and on the undoped oxide barrier in the periphery circuit area.

Abstract translation: 本发明涉及一种半导体器件，其分别包括位于衬底的存储器阵列区域和外围电路区域中的至少一个栅极，其中存储器阵列区域中的图案密度高于外围电路区域中的图案密度 。 半导体器件还包括位于存储器阵列区域和外围电路区域中的阻挡层，位于外围电路区域中的阻挡层上的未掺杂的氧化物屏障和含硼硅酸盐玻璃，其中 位于存储器阵列区域中的阻挡层上和外围电路区域中未掺杂的氧化物屏障上。

公开(公告)号：US08599633B2

公开(公告)日：2013-12-03

申请号：US13464998

申请日：2012-05-06

Applicant: Ming-Sheng Tung

Inventor： Ming-Sheng Tung

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C11/4091 ,  G11C11/4094

Abstract: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.

Abstract translation: 半导体存储器件包括存储单元，感测放大器，预充电电路和控制信号发生器。 预充电电路具有NMOS晶体管和两个PMOS晶体管，并且用于对位线对的位线进行预充电，其中NMOS晶体管由第一控制信号控制，并且两个PMOS晶体管由第二控制信号控制。 控制信号发生器用于产生第一和第二控制信号，其中仅当第二控制信号处于第一逻辑低电平时，第一控制信号处于逻辑高电平，第一控制信号处于逻辑低电平 当第二控制信号处于第二逻辑低电平或第一逻辑高电平，并且第二逻辑低电平高于第一逻辑低电平时。

公开(公告)号：US20130307515A1

公开(公告)日：2013-11-21

申请号：US13476520

申请日：2012-05-21

Applicant: Ming-Sheng Tung

Inventor： Ming-Sheng Tung

IPC: G05F3/02

CPC classification number: G05F3/30

Abstract: The present invention discloses a circuit for generating a dual-mode proportional to absolute temperature (PTAT) current. The circuit includes a voltage stabilizing circuit to provide a voltage reference, and a load current control circuit comprising a first transistor to provide a first load current based on the voltage reference, a second transistor to provide a second load current based on the voltage reference, a first switch to control whether to allow the first load current to flow therethrough in response to different predetermined temperatures, and a second switch to control whether to allow the second load current to flow therethrough in response to the different predetermined temperatures. A resultant current resulting from at least one of the first load current or the second load current has different current magnitudes at the different predetermined temperatures.

Abstract translation: 本发明公开了一种用于产生与绝对温度（PTAT）电流成比例的双模的电路。 该电路包括用于提供电压参考的稳压电路和负载电流控制电路，该负载电流控制电路包括第一晶体管，以基于该参考电压提供第一负载电流;第二晶体管，用于基于该电压基准提供第二负载电流， 用于响应于不同的预定温度控制是否允许第一负载电流流过其中的第一开关，以及响应于不同的预定温度来控制是否允许第二负载电流流过其中的第二开关。 由第一负载电流或第二负载电流中的至少一个产生的合成电流在不同的预定温度下具有不同的电流幅值。

公开(公告)号：US08575912B1

公开(公告)日：2013-11-05

申请号：US13476520

申请日：2012-05-21

Applicant: Ming-Sheng Tung

Inventor： Ming-Sheng Tung

IPC: G05F3/16

CPC classification number: G05F3/30

Abstract: The present invention discloses a circuit for generating a dual-mode proportional to absolute temperature (PTAT) current. The circuit includes a voltage stabilizing circuit to provide a voltage reference, and a load current control circuit comprising a first transistor to provide a first load current based on the voltage reference, a second transistor to provide a second load current based on the voltage reference, a first switch to control whether to allow the first load current to flow therethrough in response to different predetermined temperatures, and a second switch to control whether to allow the second load current to flow therethrough in response to the different predetermined temperatures. A resultant current resulting from at least one of the first load current or the second load current has different current magnitudes at the different predetermined temperatures.

Abstract translation: 本发明公开了一种用于产生与绝对温度（PTAT）电流成比例的双模的电路。 该电路包括用于提供电压参考的稳压电路和负载电流控制电路，该负载电流控制电路包括第一晶体管，以基于该参考电压提供第一负载电流;第二晶体管，用于基于该电压基准提供第二负载电流， 用于响应于不同的预定温度控制是否允许第一负载电流流过其中的第一开关，以及响应于不同的预定温度来控制是否允许第二负载电流流过其中的第二开关。 由第一负载电流或第二负载电流中的至少一个产生的合成电流在不同的预定温度下具有不同的电流幅值。

公开(公告)号：US07427569B2

公开(公告)日：2008-09-23

申请号：US11307801

申请日：2006-02-23

Applicant: Tza-Hao Wang ,  Jin-Yang Huang ,  Hung-Kwei Liao ,  Ming-Sheng Tung

Inventor： Tza-Hao Wang ,  Jin-Yang Huang ,  Hung-Kwei Liao ,  Ming-Sheng Tung

IPC: H01L21/00 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/32139 ,  H01L21/321 ,  H01L21/32135

Abstract: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.

Abstract translation: 描述金属蚀刻工艺。 提供其上具有介电层的基板。 在电介质层上形成铝 - 铜合金层。 在铝 - 铜合金层上形成硬掩模层。 在硬掩模层上形成图案化的光致抗蚀剂层，然后对硬掩模层进行图案化。 进行热处理工艺。 热处理过程在大于300℃的温度下进行至少3分钟的时间。 此后，使用图案化的硬掩模层作为蚀刻掩模蚀刻铝 - 铜合金层。 由于热处理，铝 - 铜合金层内的金属沉淀物（CuAl 2 N 2）被消除，因此改善了金属蚀刻工艺。