知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.01 seconds)

    3D chip arrangement including memory manager
    1.
    发明授权
    3D chip arrangement including memory manager 有权
    3D芯片布置包括内存管理器

    公开(公告)号：US07894229B2

    公开(公告)日：2011-02-22

    申请号：US12343223

    申请日：2008-12-23

    Applicant: Vesa Lahtinen ,  Tapio Hill ,  Kimmo Kuusilinna ,  Jari Nikara ,  Mika Kuulusa ,  Tommi Makelainen

    Inventor： Vesa Lahtinen ,  Tapio Hill ,  Kimmo Kuusilinna ,  Jari Nikara ,  Mika Kuulusa ,  Tommi Makelainen

    IPC: G11C5/02

    CPC classification number: G11C5/025 ,  G11C5/02 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

    Abstract: Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.

    Abstract translation: 涉及集中式存储器管理的系统，装置和方法能够动态分配和分配所有子系统的存储器。 一个实施例涉及基底基板，基底基板上的逻辑管芯，并具有子系统，具有存储器模块的存储管芯，存储器管理单元，第一数据接口，其将 具有所述至少一个逻辑管芯的存储器管理单元，将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口，将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口，其中所述配置接口包括面 面对连接，将存储器管理单元与至少一个逻辑管芯连接的控制接口，其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上，并且存储器 管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问，并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块 一个配置界面。

    Message transmitted automatically in response to imminent power source depletion of mobile station
    2.
    发明申请
    Message transmitted automatically in response to imminent power source depletion of mobile station 有权
    响应于移动台即将来临的电源耗尽自动发送消息

    公开(公告)号：US20090325613A1

    公开(公告)日：2009-12-31

    申请号：US12215634

    申请日：2008-06-27

    Applicant: Mika Kuulusa ,  Juha Kuulusa

    Inventor： Mika Kuulusa ,  Juha Kuulusa

    IPC: H04Q7/20

    CPC classification number: H04W4/16 ,  G01R31/3689 ,  H01M10/48 ,  H04M1/72547 ,  H04W4/14 ,  H04W52/0261 ,  Y02D70/122 ,  Y02D70/164 ,  Y02D70/23

    Abstract: Described herein are a method, apparatus and computer program to automatically inform a second party to a call that a first party to the call has or will disconnect due to a power source, such as a battery, of a terminal used by the first party becoming depleted. The second party can be informed by the generation and transmission of any suitable type of message, including a SMS message, a MMS message and a IMS message.

    Abstract translation: 这里描述的是一种方法，装置和计算机程序，用于自动通知第二方呼叫，呼叫的第一方由于第一方使用的终端所使用的终端的电源（例如电池）已经或将断开连接 耗尽 可以通过任何合适类型的消息的生成和传输来通知第二方，包括SMS消息，MMS消息和IMS消息。

    Method and Apparatus Providing for Transmission of a Content Package
    3.
    发明申请
    Method and Apparatus Providing for Transmission of a Content Package 审中-公开
    提供内容包传输的方法和装置

    公开(公告)号：US20120317489A1

    公开(公告)日：2012-12-13

    申请号：US13577369

    申请日：2010-02-09

    Applicant: Mika Kuulusa ,  Henrik Hakala ,  Aki Happonen

    Inventor： Mika Kuulusa ,  Henrik Hakala ,  Aki Happonen

    IPC: G06F15/16 ,  G06F3/01

    CPC classification number: G06F3/04883 ,  G06F3/017 ,  H04B17/24 ,  H04B17/318 ,  H04M1/7253 ,  H04W4/80

    Abstract: An apparatus for providing for improved transmission of a content package may include a gesture recognizer configured to recognize gesture inputs on a touch screen which select content for transmission. A communication interface may search for signals from accessible devices, and a received signal strength meter may determine corresponding received signal strengths. A target device selector may select a target device from the accessible devices based at least in part on the received signal strengths. The communication interface may then provide for transmission of a content package including the content and configured for reception by the target device in instances in which the target device is selected. A corresponding method and computer program product are also provided.

    Abstract translation: 用于提供内容包的改进传输的装置可以包括：手势识别器，被配置为识别选择要发送的内容的触摸屏上的手势输入。 通信接口可以搜索来自可访问设备的信号，并且接收的信号强度计可以确定相应的接收信号强度。 目标设备选择器可以至少部分地基于所接收的信号强度从可访问设备中选择目标设备。 然后，通信接口可以提供包括内容的内容包的传输，并且被配置为在目标设备被选择的情况下被目标设备接收。 还提供了相应的方法和计算机程序产品。

    3D CHIP ARRANGEMENT INCLUDING MEMORY MANAGER
    4.
    发明申请
    3D CHIP ARRANGEMENT INCLUDING MEMORY MANAGER 有权
    3D芯片安排，包括内存管理器

    公开(公告)号：US20090147557A1

    公开(公告)日：2009-06-11

    申请号：US12343223

    申请日：2008-12-23

    Applicant: VESA LAHTINEN ,  TAPIO HILL ,  KIMMO KUUSILINNA ,  JARI NIKARA ,  MIKA KUULUSA ,  TOMMI MAKELAINEN

    Inventor： VESA LAHTINEN ,  TAPIO HILL ,  KIMMO KUUSILINNA ,  JARI NIKARA ,  MIKA KUULUSA ,  TOMMI MAKELAINEN

    IPC: G11C5/02 ,  G11C5/06

    CPC classification number: G11C5/025 ,  G11C5/02 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

    Abstract: Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.

    Abstract translation: 涉及集中式存储器管理的系统，装置和方法能够动态分配和分配所有子系统的存储器。 一个实施例涉及基底基板，基底基板上的逻辑管芯，并具有子系统，具有存储器模块的存储管芯，存储器管理单元，第一数据接口，其将 具有所述至少一个逻辑管芯的存储器管理单元，将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口，将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口，其中所述配置接口包括面 面对连接，将存储器管理单元与至少一个逻辑管芯连接的控制接口，其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上，并且存储器 管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问，并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块 一个配置界面。

    3D chip arrangement including memory manager
    5.
    发明授权
    3D chip arrangement including memory manager 有权
    3D芯片布置包括内存管理器

    公开(公告)号：US07477535B2

    公开(公告)日：2009-01-13

    申请号：US11543351

    申请日：2006-10-05

    Applicant: Vesa Lahtinen ,  Tapio Hill ,  Kimmo Kuusilinna ,  Jari Nikara ,  Mika Kuulusa ,  Tommi Makelainen

    Inventor： Vesa Lahtinen ,  Tapio Hill ,  Kimmo Kuusilinna ,  Jari Nikara ,  Mika Kuulusa ,  Tommi Makelainen

    IPC: G11C5/02

    CPC classification number: G11C5/025 ,  G11C5/02 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

    Abstract: Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.

    Abstract translation: 涉及集中式存储器管理的系统，装置和方法能够动态分配和分配所有子系统的存储器。 一个实施例涉及基底基板，基底基板上的逻辑管芯，并具有子系统，具有存储器模块的存储管芯，存储器管理单元，第一数据接口，其将 具有所述至少一个逻辑管芯的存储器管理单元，将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口，将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口，其中所述配置接口包括面 面对连接，将存储器管理单元与至少一个逻辑管芯连接的控制接口，其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上，并且存储器 管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问，并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块 一个配置界面。

    METHOD AND APPARATUS FOR PROVIDING DETAILED PROGRESS INDICATORS
    6.
    发明申请
    METHOD AND APPARATUS FOR PROVIDING DETAILED PROGRESS INDICATORS 审中-公开
    提供详细进度指标的方法和装置

    公开(公告)号：US20120304098A1

    公开(公告)日：2012-11-29

    申请号：US13117856

    申请日：2011-05-27

    Applicant: Mika Kuulusa

    Inventor： Mika Kuulusa

    IPC: G06F3/048

    CPC classification number: G06F3/0481 ,  G06Q10/103 ,  G06Q30/0207 ,  G06Q50/01

    Abstract: An approach is provided for providing detailed progress indicators. A progress indicator platform determines a plurality of entities associated with performing at least one task. The progress indicator platform determines progress information for performing the at least one task. Nest, the progress indicator platform processes and/or facilitates a processing of the progress information to determine task contribution information associated with respective ones of the plurality of entities. Next, the progress indicator platform causes, at least in part, a rendering of a user interface element to depict, at least in part, the progress information, the task contribution information, or a combination thereof.

    Abstract translation: 提供了一种提供详细进度指标的方法。 进度指示器平台确定与执行至少一个任务相关联的多个实体。 进度指示器平台确定用于执行至少一个任务的进度信息。 Nest，进度指示器平台处理和/或促进进度信息的处理以确定与多个实体中的相应实体相关联的任务贡献信息。 接下来，进度指示器平台至少部分地导致用户界面元素的呈现至少部分地描绘进度信息，任务贡献信息或其组合。

    3D chip arrangement including memory manager
    8.
    发明申请
    3D chip arrangement including memory manager 有权
    3D芯片布置包括内存管理器

    公开(公告)号：US20080084725A1

    公开(公告)日：2008-04-10

    申请号：US11543351

    申请日：2006-10-05

    Applicant: Vesa Lahtinen ,  Tapio Hill ,  Kimmo Kuusilinna ,  Jari Nikara ,  Mika Kuulusa ,  Tommi Makelainen

    Inventor： Vesa Lahtinen ,  Tapio Hill ,  Kimmo Kuusilinna ,  Jari Nikara ,  Mika Kuulusa ,  Tommi Makelainen

    IPC: G11C5/02 ,  G06F15/177 ,  G06F9/24 ,  G06F9/00

    CPC classification number: G11C5/025 ,  G11C5/02 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

    Abstract: Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.

    Abstract translation: 涉及集中式存储器管理的系统，装置和方法能够动态分配和分配所有子系统的存储器。 一个实施例涉及基底基板，基底基板上的逻辑管芯，并具有子系统，具有存储器模块的存储管芯，存储器管理单元，第一数据接口，其将 具有所述至少一个逻辑管芯的存储器管理单元，将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口，将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口，其中所述配置接口包括面 面对连接，将存储器管理单元与至少一个逻辑管芯连接的控制接口，其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上，并且存储器 管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问，并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块 一个配置界面。

Patent Agency Ranking