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1.发明授权公开(公告)号：US08514112B2
公开(公告)日：2013-08-20
申请号：US13168017
申请日：2011-06-24
申请人： Roderick McLachlan , Michael Coln
发明人： Roderick McLachlan , Michael Coln
IPC分类号： H03M1/06
CPC分类号： H03M1/0621 , H03M1/1047 , H03M1/804 , H03M1/808
摘要： The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal.
摘要翻译： 本发明提供耦合到转换器的系统误差校正网络。 转换器可能会显示系统的非线性误差，并且系统误差校正网络对于非线性误差，形成像反失真函数一样的校正变换函数。 然后，系统误差校正网络根据参考变量对校正变换函数进行缩放，其中非线性误差的大小与参考变量相关。 然后将缩放的校正变换函数应用于转换器路径，以便产生校正的模拟输出信号。
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2.发明申请公开(公告)号：US20120013492A1
公开(公告)日：2012-01-19
申请号：US13168017
申请日：2011-06-24
申请人： Roderick MCLACHLAN , Michael COLN
发明人： Roderick MCLACHLAN , Michael COLN
IPC分类号： H03M1/06
CPC分类号： H03M1/0621 , H03M1/1047 , H03M1/804 , H03M1/808
摘要： The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal.
摘要翻译： 本发明提供耦合到转换器的系统误差校正网络。 转换器可能会显示系统的非线性误差，并且系统误差校正网络对于非线性误差，形成像反失真函数一样的校正变换函数。 然后，系统误差校正网络根据参考变量对校正变换函数进行缩放，其中非线性误差的大小与参考变量相关。 然后将缩放的校正变换函数应用于转换器路径，以便产生校正的模拟输出信号。
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公开(公告)号：US20110043251A1
公开(公告)日：2011-02-24
申请号：US12630999
申请日：2009-12-04
申请人： Yoshinori Kusuda , Michael Coln , Gary Carreau
发明人： Yoshinori Kusuda , Michael Coln , Gary Carreau
IPC分类号： H03K19/00
CPC分类号： H03M1/0818 , H03M1/1225
摘要： An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.
摘要翻译： 集成电路可以包括多个电路子系统，其包括在相应的临界相位和非临界相位操作中操作的至少一个转换器电路，具有用于外部提供的时钟信号的输入的时钟分配电路是有效的 在非临界阶段期间在关键阶段期间不起作用，以及时钟发生器，用于在外部提供的时钟信号无效时，向转换器电路产生内部时钟信号，该转换器电路有效。
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公开(公告)号：US20110038083A1
公开(公告)日：2011-02-17
申请号：US12647067
申请日：2009-12-24
申请人： Michael COLN , Gary CARREAU , Yoshinori KUSUDA
发明人： Michael COLN , Gary CARREAU , Yoshinori KUSUDA
IPC分类号： H02H9/00
CPC分类号： H01L27/0255
摘要： Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node.
摘要翻译： 公开的实施例涉及电过载保护电路。 电过载保护电路可以包括接收参考电压的中间节点，具有相反极性的第一对钳位装置，将输入信号线钳位到中间节点，以及第二对钳位装置，每个钳位装置将中间节点夹紧到 两个参考电位之一。 电过载保护电路还可以包括连接到中间节点的滤波器以减少中间节点处的噪声。
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公开(公告)号：US08514014B2
公开(公告)日：2013-08-20
申请号：US13023751
申请日：2011-02-09
IPC分类号： H03F1/02
CPC分类号： H03F1/34 , H03F3/45475 , H03F3/68 , H03F2203/45514
摘要： An amplifier system can include a feedback amplifier circuit having an amplifier, a feedback capacitor connected between an input terminal and an output terminal of the amplifier by at least one first switch, and a reset capacitor connected across the feedback capacitor by at least one second switch and between a pair of reference voltages by at least one third switch. During an input-signal processing phase of operation, a control circuit may close the at least one first switch and open the at least one second switch to electrically connect the feedback capacitor between the input and output terminals to engage feedback processing by the feedback amplifier circuit, and close the third switch to electrically connect the reset capacitor between the first and second voltages to charge the reset capacitor to a selectable voltage difference. During a reset phase of operation, the control circuit may open the at least one third switch, close the at least one second switch and open the at least one first switch to electrically connect the reset capacitor across the feedback capacitor to reset the feedback capacitor using the reset capacitor. The amplifier system can optionally include a plurality of the feedback amplifier circuits.
摘要翻译： 放大器系统可以包括具有放大器的反馈放大器电路，通过至少一个第一开关连接在放大器的输入端子和输出端子之间的反馈电容器以及通过至少一个第二开关连接在反馈电容器上的复位电容器 以及通过至少一个第三开关在一对参考电压之间。 在操作的输入信号处理阶段期间，控制电路可以关闭所述至少一个第一开关并且打开所述至少一个第二开关以将所述反馈电容器电连接在所述输入和输出端子之间，以接收所述反馈放大器电路的反馈处理 并且关闭第三开关以在第一和第二电压之间电连接复位电容器，以将复位电容器充电至可选择的电压差。 在复位操作阶段期间，控制电路可以打开至少一个第三开关，闭合至少一个第二开关并且打开至少一个第一开关，以使反复电容器上的复位电容器电连接以使反馈电容器复位，以使用 复位电容。 放大器系统可以可选地包括多个反馈放大器电路。
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公开(公告)号：US20130119502A1
公开(公告)日：2013-05-16
申请号：US13297571
申请日：2011-11-16
IPC分类号： H01L27/144 , H01L27/06
CPC分类号： H01L29/0646 , H01L23/481 , H01L27/0255 , H01L27/1446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.
摘要翻译： 形成在衬底上的半导体器件包括第一二极管结形成，第二二极管结形成以及至少一个通硅通孔（TSV），其中第一二极管的阴极和阳极交叉连接到 通过至少一个TSV来实现第二二极管的阳极和阴极，以实现基于硅通孔的集成电路中的电鲁棒性，包括用于信号处理应用的光敏器件和电路。
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公开(公告)号：US20130070805A1
公开(公告)日：2013-03-21
申请号：US13561711
申请日：2012-07-30
申请人： Michael COLN , Alain Valentin GUERY , Lejun HU
发明人： Michael COLN , Alain Valentin GUERY , Lejun HU
CPC分类号： G01K7/186 , G01K15/005 , G01K2217/00 , G01K2219/00
摘要： An accurate, cost-efficient temperature sensor may be integrated into an integrated circuit (IC) using common materials as the IC's interconnect metallization. The temperature sensor may include an impedance element having a length of metal made of the interconnect metal, a current source connected between a first set of contacts at opposite ends of the impedance element, and an analog-to-digital converter connected between a second set of contacts at opposite ends of the impedance element. The temperature sensor may exploits the proportional relationship between the metal's resistance and temperature to measure ambient temperature. Alternatively, such a temperature sensor may be used on disposable chemical sensors where the impedance element is made of a common metal as conductors that connect a sensor reactant to sensor contacts. In either case, because the impedance element is formed of a common metal as other interconnect, it is expected to incur low manufacturing costs.
摘要翻译： 使用普通材料作为IC的互连金属化，可将精确的，具有成本效益的温度传感器集成到集成电路（IC）中。 温度传感器可以包括具有由互连金属制成的金属长度的阻抗元件，连接在阻抗元件的相对端处的第一组触点之间的电流源和连接在第二组之间的模数转换器 的阻抗元件的相对端处的触点。 温度传感器可以利用金属电阻和温度之间的比例关系来测量环境温度。 或者，这种温度传感器可以用在一次性化学传感器上，其中阻抗元件由公共金属制成，作为将传感器反应物连接到传感器触点的导体。 在任一种情况下，由于阻抗元件由作为其他互连的公共金属形成，所以预期会导致低的制造成本。
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公开(公告)号：US20110304488A1
公开(公告)日：2011-12-15
申请号：US12846649
申请日：2010-07-29
申请人： Lalinda FERNANDO , Michael COLN
发明人： Lalinda FERNANDO , Michael COLN
IPC分类号： H03M1/48
CPC分类号： H03M1/0626 , H03M1/645
摘要： A system and method for reducing noise in resolver-to-digital converters (RDC) using a cascaded tracking loop filter. In some embodiments, one or more tracking loop filters may be implemented in a cascade to attenuate carrier harmonic frequencies in the digitized output of an RDC. Where a plurality of tracking loop filters are implemented, the output of one tracking loop filter may be input into a successive tracking loop filter.
摘要翻译： 一种使用级联跟踪环路滤波器降低分解数字转换器（RDC）中噪声的系统和方法。 在一些实施例中，可以级联地实现一个或多个跟踪环路滤波器，以衰减RDC的数字化输出中的载波谐波频率。 在实现多个跟踪环路滤波器的情况下，一个跟踪环路滤波器的输出可被输入到连续的跟踪环路滤波器中。
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公开(公告)号：US5666299A
公开(公告)日：1997-09-09
申请号：US446036
申请日：1995-05-19
申请人： Robert W. Adams , Tom W. Kwan , Michael Coln
发明人： Robert W. Adams , Tom W. Kwan , Michael Coln
CPC分类号： H03H17/0628
摘要： An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.
摘要翻译： 异步数字采样率转换器包括用于存储输入数据值的随机存取存储器和用于存储缩减的一组内插滤波器系数的只读存储器。 输入数据以输入采样率写入随机存取存储器。 输出样本由给定输入数据流的乘法/累加引擎提供，滤波器系数根据请求在输出频率下产生输出采样。 用于从随机存取存储器读取输入数据的初始地址和来自只读存储器的系数的地址由自动定心方案提供，该自动定心方案是具有通过输入的近似馈送的数字积分器的一阶闭环系统 输出采样率。 这种自动对中方案可以包括用于消除稳态误差的前馈低通滤波器和内插写入地址以减少噪声。 还可以提供确定输入到输入采样速率比的电路，以缩放系数地址和产生的输出采样以允许抽取。 该电路包括一种消除噪声的数字滞后形式。 通过依赖于内插滤波器的脉冲响应的对称性以及利用可变步长前后线性插值来减小ROM系数。
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公开(公告)号：US5471411A
公开(公告)日：1995-11-28
申请号：US234177
申请日：1994-04-28
申请人： Robert W. Adams , Tom W. Kwan , Michael Coln
发明人： Robert W. Adams , Tom W. Kwan , Michael Coln
CPC分类号： H03H17/0628
摘要： An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.
摘要翻译： 异步数字采样率转换器包括用于存储输入数据值的随机存取存储器和用于存储缩减的一组内插滤波器系数的只读存储器。 输入数据以输入采样率写入随机存取存储器。 输出样本由给定输入数据流的乘法/累加引擎提供，滤波器系数根据请求在输出频率下产生输出采样。 用于从随机存取存储器读取输入数据的初始地址和来自只读存储器的系数的地址由自动定心方案提供，该自动定心方案是具有通过输入的近似馈送的数字积分器的第一阶闭环系统 输出采样率。 这种自动对中方案可以包括用于消除稳态误差的前馈低通滤波器和内插写入地址以减少噪声。 还可以提供确定输入到输入采样速率比的电路，以缩放系数地址和产生的输出采样以允许抽取。 该电路包括一种消除噪声的数字滞后形式。 通过依赖于内插滤波器的脉冲响应的对称性以及利用可变步长前后线性插值来减小ROM系数。
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