知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.016 秒)

    Process for damascene structure with reduced low-k damage
    1.
    发明授权
    Process for damascene structure with reduced low-k damage 有权
    具有降低低k损伤的镶嵌结构的工艺

    公开(公告)号：US08951911B2

    公开(公告)日：2015-02-10

    申请号：US13174621

    申请日：2011-06-30

    申请人： Mehul B. Naik ,  Zhenjiang Cui

    发明人： Mehul B. Naik ,  Zhenjiang Cui

    IPC分类号： H01L21/44 ,  H01L21/02 ,  H01L21/768

    CPC分类号： H01L21/02697 ,  H01L21/7681 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76873 ,  H01L21/76885 ,  H01L29/66583

    摘要： Embodiments described herein generally provide methods for reducing undesired low-k damages during a damascene process using a sacrificial dielectric material and optionally a barrier/capping layer. In one embodiment, a damascene structure is formed through a sacrificial dielectric material deposited over a dielectric base layer. The damascene structure is filled with a suitable metal such as copper. The sacrificial dielectric material filled in trench areas between the copper damascene is then removed, followed by a barrier/cap layer which conformally or selectively covers exposed surfaces of the copper damascene structure. Ultra low-k dielectric materials may then fill the trench areas that were previously filled with sacrificial dielectric material. The invention prevents the ultra low-k material between the metal lines from exposing to various damaging processes during a damascene process such as etching, stripping, wet cleaning, pre-metal cleaning or CMP process.

    摘要翻译： 本文描述的实施例通常提供用于在使用牺牲介电材料和任选的阻挡/覆盖层的镶嵌工艺期间减少不希望的低k损伤的方法。 在一个实施例中，通过沉积在电介质基底层上的牺牲绝缘材料形成镶嵌结构。 镶嵌结构填充有合适的金属如铜。 填充在铜镶嵌之间的沟槽区域中的牺牲介电材料然后被去除，随后是保形或选择性地覆盖铜镶嵌结构的暴露表面的阻挡层/盖层。 然后，超低k电介质材料可以填充先前填充有牺牲介电材料的沟槽区域。 本发明防止金属线之间的超低k材料在蚀刻，剥离，湿法清洗，金属前清洗或CMP工艺的大马士革处理过程中暴露于各种破坏性工艺。

    PROCESS FOR DAMASCENE STRUCTURE WITH REDUCED LOW-K DAMAGE
    3.
    发明申请
    PROCESS FOR DAMASCENE STRUCTURE WITH REDUCED LOW-K DAMAGE 有权
    具有减少低K损伤的耐磨结构的方法

    公开(公告)号：US20120252206A1

    公开(公告)日：2012-10-04

    申请号：US13174621

    申请日：2011-06-30

    申请人： MEHUL B. NAIK ,  Zhenjiang Cui

    发明人： MEHUL B. NAIK ,  Zhenjiang Cui

    IPC分类号： H01L21/768

    CPC分类号： H01L21/02697 ,  H01L21/7681 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76873 ,  H01L21/76885 ,  H01L29/66583

    摘要： Embodiments described herein generally provide methods for reducing undesired low-k damages during a damascene process using a sacrificial dielectric material and optionally a barrier/capping layer. In one embodiment, a damascene structure is formed through a sacrificial dielectric material deposited over a dielectric base layer. The damascene structure is filled with a suitable metal such as copper. The sacrificial dielectric material filled in trench areas between the copper damascene is then removed, followed by a barrier/cap layer which conformally or selectively covers exposed surfaces of the copper damascene structure. Ultra low-k dielectric materials may then fill the trench areas that were previously filled with sacrificial dielectric material. The invention prevents the ultra low-k material between the metal lines from exposing to various damaging processes during a damascene process such as etching, stripping, wet cleaning, pre-metal cleaning or CMP process.

    摘要翻译： 本文描述的实施例通常提供用于在使用牺牲介电材料和任选的阻挡/覆盖层的镶嵌工艺期间减少不希望的低k损伤的方法。 在一个实施例中，通过沉积在电介质基底层上的牺牲绝缘材料形成镶嵌结构。 镶嵌结构填充有合适的金属如铜。 填充在铜镶嵌之间的沟槽区域中的牺牲介电材料然后被去除，随后是保形或选择性地覆盖铜镶嵌结构的暴露表面的阻挡层/盖层。 然后，超低k电介质材料可以填充先前填充有牺牲介电材料的沟槽区域。 本发明防止金属线之间的超低k材料在蚀刻，剥离，湿法清洗，金属前清洗或CMP工艺的大马士革处理过程中暴露于各种破坏性工艺。

    Integrated circuit interconnect lines having sidewall layers
    8.
    发明授权
    Integrated circuit interconnect lines having sidewall layers 失效
    具有侧壁层的集成电路互连线

    公开(公告)号：US06391771B1

    公开(公告)日：2002-05-21

    申请号：US09121236

    申请日：1998-07-23

    申请人： Mehul B. Naik ,  Suketu A. Parikh

    发明人： Mehul B. Naik ,  Suketu A. Parikh

    IPC分类号： H01L2144

    CPC分类号： H01L23/53233 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides Cu lines which are enclosed within Cu diffusion barrier layers, for IC structures such as semiconductor devices. The Cu lines (310) have conventional top (316) and bottom (318) Cu diffusion barrier layers and novel sidewall layers (324 and 326) comprising Cu diffusion barrier materials. The present invention also provides for conductive interconnect lines for semiconductor devices which compensate partly or completely for a misalignment between the line etch pattern and the underlying contact element, such as a via plug. The misalignment tolerant line (430) is formed by fabricating novel sidewalls (438 and 440) on the line wherein the sidewalls have a thickness which equals or exceeds the width of the gap (431) which is caused by the misalignment. The misalignment tolerant line compensates for the misalignment gap and thereby prevents etching a trench in the contact element. Trench formation is reduced rather than prevented when the sidewall is thinner than the width of the misalignment gap. In additional embodiments, manufacturing systems (510) are provided for fabricating the structures of the present invention. These systems include a controller (500) which is adapted for interacting with a plurality of fabrication stations (520, 522, 524, 526 and 528).

    摘要翻译： 本发明提供了用于诸如半导体器件的IC结构的包围在Cu扩散阻挡层内的Cu线。 Cu线（310）具有常规的顶部（316）和底部（318）Cu扩散阻挡层和包含Cu扩散阻挡材料的新颖侧壁层（324和326）。 本发明还提供用于半导体器件的导电互连线，其部分地或完全地补偿线蚀刻图案和下面的接触元件（例如通孔插头）之间的未对准。 通过在线路上制造新颖的侧壁（438和440）形成不对准容限线（430），其中侧壁具有等于或超过由未对准引起的间隙（431）的宽度的厚度。 不对准容限线补偿了不对准间隙，从而防止蚀刻接触元件中的沟槽。 当侧壁比不对准间隙的宽度更薄时，减小沟槽形成而不是防止沟槽形成。 在另外的实施例中，提供制造系统（510）用于制造本发明的结构。 这些系统包括适于与多个制造站（520,522,524,526和528）相互作用的控制器（500）。

    Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics
    9.
    发明授权
    Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics 有权
    使用具有不同蚀刻特性的电介质层由双镶嵌线形成的互连线

    公开(公告)号：US06514671B1

    公开(公告)日：2003-02-04

    申请号：US09675989

    申请日：2000-09-29

    申请人： Suketu A. Parikh ,  Mehul B. Naik ,  Samuel Broydo ,  H. Peter W. Hey

    发明人： Suketu A. Parikh ,  Mehul B. Naik ,  Samuel Broydo ,  H. Peter W. Hey

    IPC分类号： G03C500

    CPC分类号： H01L21/76808 ,  H01L23/485 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (332 and 334) are formed in consecutive dielectric layers (314 and 316) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask (622) upon exposure to radiation. In additional embodiments, manufacturing systems (710) are provided for fabricating IC structures. These systems include a controller (700) which is adapted for interacting with a plurality of fabrication stations (720, 722, 724, 726, 728 and 730).

    摘要翻译： 本发明提供集成电路制造方法和装置，其中双镶嵌结构（332和334）形成在具有不同蚀刻特性的连续介电层（314和316）中。 本发明还提供了这样的方法和装置，其中这些介电层具有不同的介电常数。 本发明的另外的实施方案包括使用单层掩模，例如在暴露于辐射时形成硬掩模（622）的硅基感光材料。 在另外的实施例中，制造系统（710）用于制造IC结构。 这些系统包括适于与多个制造站（720,722,724,726,728和730）相互作用的控制器（700）。