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    Contents reproduction device
    2.
    发明申请
    Contents reproduction device 审中-公开
    内容再现设备

    公开(公告)号：US20060236145A1

    公开(公告)日：2006-10-19

    申请号：US11214868

    申请日：2005-08-31

    Applicant: Takafumi Yuasa ,  Yukio Fujii ,  Kazuhiko Tanaka ,  Koji Hosogi ,  Hiroaki Nakata ,  Masakazu Ehama

    Inventor： Takafumi Yuasa ,  Yukio Fujii ,  Kazuhiko Tanaka ,  Koji Hosogi ,  Hiroaki Nakata ,  Masakazu Ehama

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/3265 ,  Y02D10/153

    Abstract: A contents reproduction device realizes reduction of power consumption by controlling power supply control according to the input contents. More specifically, in the contents reproduction device, the PSI analysis unit analyzes additional information in the inputted contents so as to check whether video contents are contained or the signal detection unit checks whether the inputted contents contain a video signal. According to the check result, the video information detection unit detects whether the inputted contents contain video information and outputs the detection result to the power control unit. When the inputted contents contain video information, the power control unit supplies power to the display. When no video information is contained, the power control unit stops power supply to the display and turns off power supply to the display.

    Abstract translation: 内容再现装置通过根据输入内容控制电源控制来实现功耗的降低。 更具体地，在内容再现装置中，PSI分析单元分析输入的内容中的附加信息，以便检查视频内容是否包含，或者信号检测单元检查输入的内容是否包含视频信号。 根据检查结果，视频信息检测单元检测输入的内容是否包含视频信息，并将检测结果输出到电源控制单元。 当输入的内容包含视频信息时，电源控制单元向显示器供电。 当没有包含视频信息时，电源控制单元停止对显示器的电力供应，并且关闭对显示器的电源。

    Image processing device, decoding method, intra-frame decoder, method of decoding intra-frame and intra-frame encoder
    4.
    发明授权
    Image processing device, decoding method, intra-frame decoder, method of decoding intra-frame and intra-frame encoder 有权
    图像处理装置，解码方法，帧内解码器，帧内编码方式和帧内编码方式

    公开(公告)号：US09503728B2

    公开(公告)日：2016-11-22

    申请号：US13144546

    申请日：2009-01-15

    Applicant: Seiji Mochizuki ,  Yutaka Funabashi ,  Junichi Kimura ,  Masakazu Ehama

    Inventor： Seiji Mochizuki ,  Yutaka Funabashi ,  Junichi Kimura ,  Masakazu Ehama

    IPC: H04N7/32 ,  H04N19/11 ,  H04N19/61 ,  H04N19/593 ,  H04N19/44 ,  H04N19/583

    CPC classification number: H04N19/11 ,  H04N19/44 ,  H04N19/583 ,  H04N19/593 ,  H04N19/61

    Abstract: Adopted is a decoder, in which on condition that a prediction block shown by vector information extracted from a data stream, and a decode-target block have an overlap where respective pixels overlay each other, pixel information of an already-decoded portion at a distance of an integer multiple of a vector provided by the vector information from the overlap is made a prediction signal instead of the overlap, and the prediction signal is added to difference image data taken from the data stream to generate reproduction image data. The decoder is adopted for an intra-frame decoder, a local decoder of an encoder, and the like. According to a fundamental rule concerning a repetitive pattern of an image, a pixel at a distance of an integer multiple is a like pixel, and therefore the process of decoding can be performed efficiently.

    Abstract translation: 采用的是一种解码器，其中在从数据流提取的向量信息所示的预测块和解码目标块具有彼此重叠的重叠的条件下，已经解码的部分的像素信息在距离 将来自重叠的向量信息提供的向量的整数倍的整数倍作为预测信号，而不是重叠，并将预测信号加到从数据流中取出的差分图像数据，以产生再现图像数据。 解码器用于帧内解码器，编码器的本地解码器等。 根据关于图像的重复图案的基本规则，整数倍的距离处的像素是相似的像素，因此可以有效地执行解码处理。

    PROCESSOR SYSTEM AND EXCEPTION PROCESSING METHOD
    5.
    发明申请
    PROCESSOR SYSTEM AND EXCEPTION PROCESSING METHOD 审中-公开
    处理器系统和异常处理方法

    公开(公告)号：US20080294878A1

    公开(公告)日：2008-11-27

    申请号：US12101437

    申请日：2008-04-11

    Applicant: Takafumi YUASA ,  Hiroaki Nakata ,  Koji Hosogi ,  Masakazu Ehama ,  Fumitaka Izuhara ,  Kazushi Akie

    Inventor： Takafumi YUASA ,  Hiroaki Nakata ,  Koji Hosogi ,  Masakazu Ehama ,  Fumitaka Izuhara ,  Kazushi Akie

    IPC: G06F9/38 ,  G06F9/302 ,  G06F9/312

    CPC classification number: G06F11/0793 ,  G06F9/30054 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4812 ,  G06F11/0721 ,  G06F2209/481

    Abstract: When an error is detected in an error detecting unit in a processor system, the error detecting unit outputs an error signal to an interrupt control unit, and the interrupt control unit outputs a value of an error address register and a control signal to a program counter control unit and rewrites a value of a program counter to a value of an error address register. By this means, the branching process by an error interrupt is realized. In this case, when the error is detected, the process of saving the value of the program counter at the time of error occurrence is not performed, and a specific save register and a control circuit for the recovery to the address at the time of the error occurrence after the end of the error processing are not provided.

    Abstract translation: 当在处理器系统中的错误检测单元中检测到错误时，错误检测单元向中断控制单元输出错误信号，并且中断控制单元向程序计数器输出错误地址寄存器和控制信号的值 控制单元，并将程序计数器的值重写为错误地址寄存器的值。 通过这种方式，实现了通过错误中断的分支过程。 在这种情况下，当检测到错误时，不执行在发生错误时保存程序计数器的值的处理，以及特定的存储寄存器和控制电路，用于恢复到发生错误时的地址 未提供错误处理结束后的错误发生。

    Arrangements having security protection
    6.
    发明授权
    Arrangements having security protection 有权
    有安全保护的安排

    公开(公告)号：US07177996B2

    公开(公告)日：2007-02-13

    申请号：US10801834

    申请日：2004-03-17

    Applicant: Masakazu Ehama ,  Kazuhiko Tanaka ,  Koji Hosogi ,  Hiroaki Nakata

    Inventor： Masakazu Ehama ,  Kazuhiko Tanaka ,  Koji Hosogi ,  Hiroaki Nakata

    IPC: G06F12/00

    CPC classification number: G06F12/1441 ,  G06F12/1027 ,  G06F12/1425

    Abstract: Security threats are reduced by providing a TLB in a bus interface unit of a media processor whose contents can be updated only from inside the media processor. The TLB checks whether an address specified by an external access request falls within access-permitted areas registered in it. If it does, an access request from outside is passed on to an inside of the media processor; otherwise, it is rejected.

    Abstract translation: 通过在媒体处理器的总线接口单元中提供TLB来减少安全威胁，其媒体处理器的内容可以仅从媒体处理器内部更新。 TLB检查由外部访问请求指定的地址是否落在其中注册的访问允许区域内。 如果是这样，则来自外部的访问请求被传递到媒体处理器的内部; 否则就被拒绝。

    MOVING IMAGE PROCESSOR AND PROCESSING METHOD FOR MOVING IMAGE
    8.
    发明申请
    MOVING IMAGE PROCESSOR AND PROCESSING METHOD FOR MOVING IMAGE 有权
    移动图像处理器和移动图像的处理方法

    公开(公告)号：US20110013696A1

    公开(公告)日：2011-01-20

    申请号：US12819394

    申请日：2010-06-21

    Applicant: Yoshitaka HIRAMATSU ,  Hiroaki NAKATA ,  Masakazu EHAMA ,  Seiji MOCHIZUKI ,  Takafumi YUASA ,  Kenichi IWATA

    Inventor： Yoshitaka HIRAMATSU ,  Hiroaki NAKATA ,  Masakazu EHAMA ,  Seiji MOCHIZUKI ,  Takafumi YUASA ,  Kenichi IWATA

    IPC: H04N7/26 ,  H04N7/32 ,  H04N11/02

    CPC classification number: H04N19/86 ,  H04N19/423 ,  H04N19/436

    Abstract: A moving image processor includes a first and a second moving image processing unit which are able to perform parallel operation, and a data transfer unit having a first buffer and a second buffer. The first moving image processing unit processes macroblocks MB00, - - - , of one row of one image sequentially, and the second moving image processing unit processes macroblocks MB10, - - - , of the next row sequentially. The first and the second moving image processors include a first and a second deblocking filters, respectively. Operation timing of the second filter is delayed by the processing time of two macroblocks, compared with operation timing of the first filter. The processing results of the first filter and the second filter are transferred to an external memory via the first buffer and the second buffer of the transfer unit.

    Abstract translation: 运动图像处理器包括能够执行并行操作的第一和第二运动图像处理单元，以及具有第一缓冲器和第二缓冲器的数据传送单元。 第一运动图像处理单元顺序地处理一行一个图像的宏块MB00，...，并且第二运动图像处理单元依次处理下一行的宏块MB10， - - - 。 第一和第二运动图像处理器分别包括第一和第二去块滤波器。 与第一滤波器的操作定时相比，第二滤波器的操作定时被延迟两个宏块的处理时间。 第一滤波器和第二滤波器的处理结果经由传送单元的第一缓冲器和第二缓冲器传送到外部存储器。

    FILTER PROCESSING MODULE AND SEMICONDUCTOR DEVICE
    9.
    发明申请
    FILTER PROCESSING MODULE AND SEMICONDUCTOR DEVICE 审中-公开
    过滤处理模块和半导体器件

    公开(公告)号：US20100211623A1

    公开(公告)日：2010-08-19

    申请号：US12705898

    申请日：2010-02-15

    Applicant: Yoshitaka HIRAMATSU ,  Hiroaki Nakata ,  Masakazu Ehama ,  Seiji Mochizuki

    Inventor： Yoshitaka HIRAMATSU ,  Hiroaki Nakata ,  Masakazu Ehama ,  Seiji Mochizuki

    IPC: G06F17/10 ,  G06F5/01

    CPC classification number: G06F17/153 ,  G06T1/20 ,  H03H17/0202

    Abstract: The present invention is directed to improve efficiency of a filter processing on an image. A filter processing module includes a filter circuit and a control circuit. The filter circuit includes: a first register capable of storing data; a first arithmetic logic unit capable of executing a first filter processing on the basis of output data of the first register; a second register capable of storing a result of the arithmetic operation of the first arithmetic logic unit; and a second arithmetic logic unit capable of executing a second filter processing on the basis of output data of the second register. The control circuit adjusts the number of pieces of data which is input per cycle in the first register in accordance with the number of taps in the first filter processing, size of an execution result of the first filter processing, and the number of second arithmetic logic units, thereby promptly completing the first filter processing.

    Abstract translation: 本发明旨在提高对图像的滤波处理的效率。 滤波器处理模块包括滤波电路和控制电路。 滤波电路包括：能够存储数据的第一寄存器; 第一算术逻辑单元，其能够基于第一寄存器的输出数据执行第一滤波处理; 第二寄存器，其能够存储第一算术逻辑单元的算术运算结果; 以及能够基于第二寄存器的输出数据执行第二滤波处理的第二算术逻辑单元。 控制电路根据第一滤波处理中的抽头数，第一滤波处理的执行结果的大小和第二算术逻辑的数量来调整在第一寄存器中每个周期输入的数据数 单位，从而及时完成第一次过滤处理。

    COMPUTING UNIT AND IMAGE FILTERING DEVICE
    10.
    发明申请
    COMPUTING UNIT AND IMAGE FILTERING DEVICE 审中-公开
    计算单元和图像滤波器件

    公开(公告)号：US20090013152A1

    公开(公告)日：2009-01-08

    申请号：US12168416

    申请日：2008-07-07

    Applicant: Masakazu EHAMA ,  Koji Hosogi ,  Seiji Mochizuki

    Inventor： Masakazu EHAMA ,  Koji Hosogi ,  Seiji Mochizuki

    IPC: G06F15/80 ,  G06F9/02

    CPC classification number: G06T1/20 ,  G06T7/223 ,  G06T2207/10016 ,  G06T2207/20021

    Abstract: A processor capable of performing a filter processing in a high speed is provided. A computing unit comprises a computer for performing a filter processing. Data supply to the computer is performed by an internal register configured by a flip-flop. Data read from the internal register is outputted to a shift register and the data is supplied to the computer per cycle. And, the computing unit comprises a mechanism for changing a filter computing direction according to a motion vector, thereby preventing performance lowering due to branched command by performing a horizontal filtering and a vertical filtering by a same command.

    Abstract translation: 提供能够高速进行滤波处理的处理器。 计算单元包括用于执行滤波处理的计算机。 通过由触发器配置的内部寄存器来执行向计算机提供的数据。 从内部寄存器读取的数据被输出到移位寄存器，并且每个周期将数据提供给计算机。 并且，计算单元包括用于根据运动矢量改变滤波器计算方向的机构，从而通过执行水平滤波和通过相同命令的垂直滤波来防止由分支命令引起的性能降低。

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