公开(公告)号：US06334191B1

公开(公告)日：2001-12-25

申请号：US09575045

申请日：2000-05-19

申请人： Rollie Morris Fisher ,  Samuel James Guido ,  Martin G. Gravenstein ,  Michael Anthony Viigil

发明人： Rollie Morris Fisher ,  Samuel James Guido ,  Martin G. Gravenstein ,  Michael Anthony Viigil

IPC分类号： G06F100

CPC分类号： G06F9/4881 ,  G06F9/3851

摘要： A multi-function timer used to perform multiple input timing measurements and generate multiple timed output events on the I/O pins of the apparatus. The multi-function timer comprises a plurality of slots and a compute engine. Each of the slots represents one of a plurality of timing processes. The compute engine includes a micro-sequencer and a processor. The micro-sequencer identifies a current slot and associated plurality of instructions representing a process, and is configured to serially sequence through each of the slots. The processor performs the functions of the instructions associated with each current slot. Further, each slot is configured to perform any one of the following timing processes: pulse width modulation, high speed input, high speed output, or delta time input. The multi-function timer is advantageous in that it provides application design flexibility by eliminating the need for dedicated logic for input and output timing functions.

摘要翻译： 多功能定时器用于执行多个输入定时测量，并在设备的I / O引脚上产生多个定时输出事件。 多功能定时器包括多个时隙和计算引擎。 每个时隙表示多个定时处理中的一个。 计算引擎包括微定序器和处理器。 微定序器识别当前时隙和表示进程的相关联的多个指令，并且被配置为串行地顺序通过每个时隙。 处理器执行与每个当前时隙相关联的指令的功能。 此外，每个时隙被配置为执行以下定时处理中的任何一个：脉冲宽度调制，高速输入，高速输出或增量时间输入。 多功能定时器的优点在于它通过消除对输入和输出定时功能的专用逻辑的需要来提供应用设计的灵活性。

公开(公告)号：US06381532B1

公开(公告)日：2002-04-30

申请号：US09665094

申请日：2000-09-20

申请人： Gary T. Bastian ,  Kevin M. Rishavy ,  Martin G. Gravenstein ,  Robert L. Anderson ,  Rollie M. Fisher ,  Raymond A. Stevens ,  Samuel J. Guido

发明人： Gary T. Bastian ,  Kevin M. Rishavy ,  Martin G. Gravenstein ,  Robert L. Anderson ,  Rollie M. Fisher ,  Raymond A. Stevens ,  Samuel J. Guido

IPC分类号： G06F1310

CPC分类号： G06F13/4059

摘要： An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

摘要翻译： 一种发动机控制系统，包括与数据总线可操作地通信的主处理器和用于通信发动机操作参数的多个外围设备。 每个外围设备包括用于存储对应的多个外围设备中的每一个的通信参数的第一和第二事务寄存器。 控制系统还包括排队端口速率寄存器（QRR），其包括与多个外围设备进行操作通信的存储器单元，用于根据第一和第二事务寄存器存储用于传输到多个外围设备的数据。 该系统还包括与多个外围设备中的每一个操作通信的外围计数器。 周边计数器适于询问多个外围设备中的每一个，并且当数据已被写入外围设备之一时，根据存储器单元数据来更新外围设备。

公开(公告)号：US5799182A

公开(公告)日：1998-08-25

申请号：US786585

申请日：1997-01-21

申请人： Martin G. Gravenstein ,  Michael A. Vigil ,  Silvia E. Jaeckel

发明人： Martin G. Gravenstein ,  Michael A. Vigil ,  Silvia E. Jaeckel

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F9/30

CPC分类号： G06F9/4843 ,  G06F9/3851

摘要： A micro-sequencer apparatus (10) allows a plurality of threads to independently process one or several algorithms using common components by allowing each thread to execute one instruction during a cycle. A thread counter (12) identifies the current thread to allow processing of its instruction. A thread program counter (16) stores the program count or address for the current instruction for the current thread. An instruction memory (20) stores all instructions, and the program count identifies the particular instruction for processing. A processor (26) receives input information unique to the current thread and processes same with the current instruction to produce an output.

摘要翻译： 微定序器装置（10）允许多个线程通过允许每个线程在一个周期期间执行一个指令来使用公共部件独立地处理一个或多个算法。 线程计数器（12）识别当前线程以允许处理其指令。 线程程序计数器（16）存储当前线程的当前指令的程序计数或地址。 指令存储器（20）存储所有指令，并且程序计数识别用于处理的特定指令。 处理器（26）接收当前线程唯一的输入信息并且处理与当前指令相同的输出信息以产生输出。

公开(公告)号：US4987387A

公开(公告)日：1991-01-22

申请号：US404793

申请日：1989-09-08

申请人： Richard A. Kennedy ,  Seyed R. Zarabadi ,  Stephen L. Inman ,  Martin G. Gravenstein

发明人： Richard A. Kennedy ,  Seyed R. Zarabadi ,  Stephen L. Inman ,  Martin G. Gravenstein

IPC分类号： H03L7/089 ,  H03L7/093 ,  H03L7/18

CPC分类号： H03L7/0891 ,  H03L7/093 ,  H03L7/18

摘要： A Phase Locked Loop (PLL) circuit includes a control signal generator, a digital phase detector, logic gates, a charge pump (charge/discharge circuit), a transmission gate, a loop filter, a lead-lag filter and a voltage controlled oscillator (VCO). Outputs of the digital phase detector are coupled through the logic gates to inputs of the charge pump. An output of the charge pump is coupled to the capacitor and to a first input/output of the transmission gate. A second input/output of the transmission gate is coupled to an input of the loop filter whose output is coupled to an input of the VCO whose output is coupled to a first input of the digital phase detector. A second input of the digital phase detector is coupled to a source of a reference frequency signal. The control signal generator generates non-overlapping complementary control signals with one of same connected to the logic gates and the other connected to the transmission gate. Accordingly, the electrical path from the digital phase detector to the charge pump through the logic gates is closed and the electrical path from the capacitor to the loop filter is open or vice versa. The loop filter includes an operational amplifier with AC feedback which is controlled by the same signal which controls the logic gates. The PLL circuit is typically formed on a single integrated circuit silicon chip using CMOS technology.

公开(公告)号：US5854922A

公开(公告)日：1998-12-29

申请号：US784884

申请日：1997-01-16

申请人： Martin G. Gravenstein ,  Michael A. Vigil ,  Silvia E. Jaeckel

发明人： Martin G. Gravenstein ,  Michael A. Vigil ,  Silvia E. Jaeckel

IPC分类号： G06F9/26 ,  G06F9/38 ,  G06F9/22

CPC分类号： G06F9/3851 ,  G06F9/26

摘要： A micro-code sequencer apparatus (10) and method includes a state machine controller (14) and an instruction memory (24) for executing instructions and branches. The branch conditions for each state are stored in the state machine controller (14) whereas reprogrammable calculation instructions are stored in instruction memory (24). The instruction memory (24) is accessed by a program counter (20) which receives the decoded state information to determine the location of its instruction. A processor (30) processes the instruction and sends the output to a next state decoder (32) which determines the next state based on the branch conditions.

摘要翻译： 微代码定序器装置（10）和方法包括一个用于执行指令和分支的状态机控制器（14）和指令存储器（24）。 每个状态的分支条件存储在状态机控制器（14）中，而可编程计算指令被存储在指令存储器（24）中。 指令存储器（24）由程序计数器（20）访问，程序计数器（20）接收解码的状态信息以确定其指令的位置。 处理器（30）处理指令并将输出发送到下一状态解码器（32），该解码器基于分支条件确定下一状态。

公开(公告)号：US06978340B2

公开(公告)日：2005-12-20

申请号：US09774230

申请日：2001-01-30

申请人： Rollie M. Fisher ,  Samuel J. Guido ,  Martin G. Gravenstein ,  Raymond A. Stevens

发明人： Rollie M. Fisher ,  Samuel J. Guido ,  Martin G. Gravenstein ,  Raymond A. Stevens

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4291

摘要： A controller 12 has an I/O crossover switching network 14, an optional I/O network expansion 16, a plurality of serial I/O shifters 18, a clock generator 20 and I/O control logic 22. The I/O crossover-switching network 14 is also referred to as an I/O multiplexer. Serial data may be transferred between a serial I/O shifter and an external device by way of a dedicated serial data pin (SDATA) 24 or an optional alternate pathway 26 which uses one of a plurality of parallel pins 28. The optional alternate pathway 26 can be used when pins 28 are unavailable or to reduce the number of pins on the device 12. The controller is shown to communicate with an external device 30 also having parallel pins 32. While a single device 30 is shown, the external device 30 can be any number of a plurality of devices having serial and parallel signal pathways that is controlled by the microprocessor 10 of the present invention.

摘要翻译： 控制器12具有I / O交叉交换网络14，可选的I / O网络扩展16，多个串行I / O移位器18，时钟发生器20和I / O控制逻辑22。 I / O交换交换网络14也称为I / O多路复用器。 串行数据可以通过专用串行数据引脚（SDATA）24或使用多个并行引脚28之一的可选的备用通路26在串行I / O移位器和外部设备之间传输。 当引脚28不可用或减少器件12上的引脚数时，可以使用可选的备选路径26。 控制器被示出为与具有并行销32的外部设备30通信。 虽然示出了单个设备30，但是外部设备30可以是具有由本发明的微处理器10控制的串行和并行信号路径的多个设备的任何数量。