摘要:
An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.
摘要:
A controller 12 has an I/O crossover switching network 14, an optional I/O network expansion 16, a plurality of serial I/O shifters 18, a clock generator 20 and I/O control logic 22. The I/O crossover-switching network 14 is also referred to as an I/O multiplexer. Serial data may be transferred between a serial I/O shifter and an external device by way of a dedicated serial data pin (SDATA) 24 or an optional alternate pathway 26 which uses one of a plurality of parallel pins 28. The optional alternate pathway 26 can be used when pins 28 are unavailable or to reduce the number of pins on the device 12. The controller is shown to communicate with an external device 30 also having parallel pins 32. While a single device 30 is shown, the external device 30 can be any number of a plurality of devices having serial and parallel signal pathways that is controlled by the microprocessor 10 of the present invention.