Queued port data controller for microprocessor-based engine control applications
    1.
    发明授权
    Queued port data controller for microprocessor-based engine control applications 失效
    排队端口数据控制器,用于基于微处理器的发动机控制应用

    公开(公告)号:US06381532B1

    公开(公告)日:2002-04-30

    申请号:US09665094

    申请日:2000-09-20

    IPC分类号: G06F1310

    CPC分类号: G06F13/4059

    摘要: An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

    摘要翻译: 一种发动机控制系统,包括与数据总线可操作地通信的主处理器和用于通信发动机操作参数的多个外围设备。 每个外围设备包括用于存储对应的多个外围设备中的每一个的通信参数的第一和第二事务寄存器。 控制系统还包括排队端口速率寄存器(QRR),其包括与多个外围设备进行操作通信的存储器单元,用于根据第一和第二事务寄存器存储用于传输到多个外围设备的数据。 该系统还包括与多个外围设备中的每一个操作通信的外围计数器。 周边计数器适于询问多个外围设备中的每一个,并且当数据已被写入外围设备之一时,根据存储器单元数据来更新外围设备。

    I/O multiplexer and pin controller with serial and parallel capabilities for microprocessor based engine control
    2.
    发明授权
    I/O multiplexer and pin controller with serial and parallel capabilities for microprocessor based engine control 失效
    I / O多路复用器和引脚控制器,具有串行和并行功能,用于基于微处理器的发动机控制

    公开(公告)号:US06978340B2

    公开(公告)日:2005-12-20

    申请号:US09774230

    申请日:2001-01-30

    IPC分类号: G06F13/42 G06F13/00

    CPC分类号: G06F13/4291

    摘要: A controller 12 has an I/O crossover switching network 14, an optional I/O network expansion 16, a plurality of serial I/O shifters 18, a clock generator 20 and I/O control logic 22. The I/O crossover-switching network 14 is also referred to as an I/O multiplexer. Serial data may be transferred between a serial I/O shifter and an external device by way of a dedicated serial data pin (SDATA) 24 or an optional alternate pathway 26 which uses one of a plurality of parallel pins 28. The optional alternate pathway 26 can be used when pins 28 are unavailable or to reduce the number of pins on the device 12. The controller is shown to communicate with an external device 30 also having parallel pins 32. While a single device 30 is shown, the external device 30 can be any number of a plurality of devices having serial and parallel signal pathways that is controlled by the microprocessor 10 of the present invention.

    摘要翻译: 控制器12具有I / O交叉交换网络14,可选的I / O网络扩展16,多个串行I / O移位器18,时钟发生器20和I / O控制逻辑22。 I / O交换交换网络14也称为I / O多路复用器。 串行数据可以通过专用串行数据引脚(SDATA)24或使用多个并行引脚28之一的可选的备用通路26在串行I / O移位器和外部设备之间传输。 当引脚28不可用或减少器件12上的引脚数时,可以使用可选的备选路径26。 控制器被示出为与具有并行销32的外部设备30通信。 虽然示出了单个设备30,但是外部设备30可以是具有由本发明的微处理器10控制的串行和并行信号路径的多个设备的任何数量。