公开(公告)号：US20060053249A1

公开(公告)日：2006-03-09

申请号：US10532260

申请日：2003-10-27

申请人： Makio Yamaki ,  Junji Oiwa

发明人： Makio Yamaki ,  Junji Oiwa

IPC分类号： G06F12/00

CPC分类号： G11B27/105 ,  G11B20/10 ,  G11B27/034 ,  G11B27/10 ,  G11B27/11 ,  G11B27/329 ,  G11B27/36 ,  G11B2220/20 ,  G11B2220/65 ,  H04N5/76 ,  H04N5/781

摘要： The present invention provides an apparatus and a method that judge whether contents recording processing is in progress and make it possible to execute reproduction processing under accurate control. A recording control process for executing contents recording processing generates reproduction synchronization management information having a reproduction synchronization management information name, which is uniquely decided from a reproduction management information name of reproduction management information, and stores the reproduction synchronization management information in a directory that is automatically erased at the time of system startup or a volatile memory that is erased at the time of power off. A reproduction control process extracts reproduction synchronization management information on the basis of a reproduction management information name and judges whether contents to be reproduced are being recorded to execute control of a reproduction process. At the time of restart after power supply interruption, the reproduction synchronization management information is reset, and the reproduction control process is prevented from performing control misunderstanding that contents are being recorded simultaneously.

摘要翻译： 本发明提供了一种判断内容记录处理是否正在进行并能够在精确控制下执行再现处理的装置和方法。 用于执行内容记录处理的记录控制处理产生具有从再现管理信息的再现管理信息名称唯一确定的再现同步管理信息名称的再现同步管理信息，并且将再现同步管理信息存储在自动的目录中 在系统启动时擦除或在断电时被擦除的易失性存储器。 再现控制处理基于再现管理信息名称提取再现同步管理信息，并且判断是否正在记录要再现的内容以执行再现处理的控制。 在电源中断之后重新启动时，再现同步管理信息被复位，并且防止再现控制处理进行同时记录内容的控制误解。

公开(公告)号：US5822775A

公开(公告)日：1998-10-13

申请号：US992648

申请日：1992-12-18

申请人： Shuhei Sudo ,  Makio Yamaki

发明人： Shuhei Sudo ,  Makio Yamaki

IPC分类号： G06F9/38 ,  G06F9/24 ,  G06F9/312 ,  G10K15/12 ,  H03H17/00 ,  H03H17/02 ,  G06F12/00

CPC分类号： G06F9/30043

摘要： A coefficient data transfer processing method for a digital signal processor which has a coefficient address pointer independent of a program counter, whereby a processing program and coefficient data are transferred and supplied from a microcomputer determination, whether an instruction is a read instruction of the coefficient data to execute a read cycle steal or with is made; a value of a program counter with is made; when it is the read instruction, new coefficient data is transferred from the microcomputer to a transfer buffer at an instruction read stage and instruction decode stage in a processing unit; and the coefficient data stored in the transfer buffer is written into a coefficient data memory by the read cycle steal at an execute stage in the same processing unit.

摘要翻译： 一种用于数字信号处理器的系数数据传送处理方法，其具有独立于程序计数器的系数地址指针，由微处理器确定传送和提供处理程序和系数数据，指令是否是系数数据的读取指令 执行读周期窃取或与之进行; 制作了一个程序计数器的值; 当读取指令时，新的系数数据从处理单元中的指令读取级和指令解码级从微型计算机传送到传送缓冲器; 并且存储在传送缓冲器中的系数数据在同一处理单元中的执行阶段通过读取周期被窃取被写入系数数据存储器。

公开(公告)号：US20050246372A1

公开(公告)日：2005-11-03

申请号：US10525664

申请日：2004-06-30

申请人： Makio Yamaki

发明人： Makio Yamaki

IPC分类号： H04N5/91 ,  G11B20/00 ,  G11B20/10 ,  G11B27/00 ,  H04N5/913 ,  H04N5/92 ,  G06F17/30

CPC分类号： H04N5/913 ,  G11B20/00086 ,  G11B20/0021 ,  G11B20/00492 ,  G11B20/00666 ,  G11B20/00673 ,  G11B20/00753 ,  G11B20/0084 ,  H04N21/4325

摘要： This invention manages temporary storage of content data according to guidelines. According to this invention, when temporary storage of a recording transport stream TS3 which is allowed to be temporarily stored in a recording medium so as to be reproducible only within a temporary storage allowable time is managed, a reproducible start point indicating a start point from which the recording transport stream TS3 can be reproduced is associated with a first time stamp out of the time stamps of the GOPs of the recording transport stream TS3, and every time when a period from a time stamp associated with the reproducible start point to the current time reaches a temporary storage allowable time, the reproducible start point is re-associated to another time stamp following the time stamp, so that an overtime part of the recording transport stream TS3 can be removed from a reproducible range so as to easily and correctly disable its reproduction, thus being capable of easily and correctly managing the temporary storage of the recording transport stream TS3.

摘要翻译： 本发明根据准则管理内容数据的临时存储。 根据本发明，在暂时存储允许临时存储在记录介质中的记录传输流TS 3仅在临时存储容许时间内被再现时，可以管理表示从 可以再现记录传输流TS 3的记录传输流TS 3的GOP的时间标记中的第一时间戳，并且每当从与可再现起始点相关联的时间戳的时间段到 当前时间达到临时存储允许时间，可重现的起始点与时间戳之后的另一个时间戳重新关联，从而可以从可再现的范围中移除记录传输流TS 3的超时部分，以便容易地 并且正确地禁止其再现，因此能够容易且正确地管理记录传输流TS 3的临时存储。

公开(公告)号：US5754874A

公开(公告)日：1998-05-19

申请号：US322353

申请日：1994-10-13

申请人： Kazuo Watanabe ,  Makio Yamaki

发明人： Kazuo Watanabe ,  Makio Yamaki

IPC分类号： G06F9/308 ,  G06F17/10 ,  G10K15/12 ,  H03H17/02 ,  H04S3/02 ,  G06F13/00

CPC分类号： H04S3/02

摘要： A digital signal processor (DSP) comprises a condition flag register directly accessible by the control microcomputer. Referring to a condition flag of the condition flag register every sampling period of the DSP, the DSP can change the content of a process every sampling period in accordance with the set status of the condition flag. The DSP sets the condition flag in the condition flag register at the beginning of a sampling period of the DSP by a set instruction, and resets the condition flag at the end of a sampling period by a reset instruction. The DSP may be modified to automatically reset the condition flag at the end of the sampling period in which the condition flag has been set.

摘要翻译： 数字信号处理器（DSP）包括可由控制微计算机直接访问的条件标志寄存器。 参考DSP的每个采样周期的条件标志寄存器的条件标志，DSP可以根据条件标志的设置状态改变每个采样周期的处理内容。 DSP通过设置指令在DSP的采样周期开始时在条件标志寄存器中设置条件标志，并在采样周期结束时通过复位指令复位条件标志。 可以修改DSP，以便在设置了条件标志的采样周期结束时自动复位条件标志。

公开(公告)号：US5218710A

公开(公告)日：1993-06-08

申请号：US467403

申请日：1990-01-22

申请人： Makio Yamaki ,  Hiroyuki Ishihara ,  Norimichi Katsumura ,  Toshiyuki Naoe ,  Yukio Matsumoto ,  Kazuhiro Hayashi ,  Kazuo Watanabe

发明人： Makio Yamaki ,  Hiroyuki Ishihara ,  Norimichi Katsumura ,  Toshiyuki Naoe ,  Yukio Matsumoto ,  Kazuhiro Hayashi ,  Kazuo Watanabe

IPC分类号： G06F17/10 ,  H03G5/02

CPC分类号： H03G5/025 ,  G06F17/10

摘要： An audio signal data processing system comprises input device for sequentially supplying an audio signal data, data memory control device for writing the audio signal data into a data memory and reading-out the data from the data memory, delay memory control device for sequentially reading-out the audio signal data from the data memory and storing the data into a location of a delay memory indicated by a writing address and for reading-out the audio signal data from a location of the delay memory indicated by a reading address and writing the data into the data memory, address designating devices for designating the writing and reading addresses, arithmetic device for multiplying a predetermined coefficient data to the audio signal data having been read-out by the delay memory control device and written into the data memory, and output device for providing the audio signal data in accordance with a result of operation by the arithmetic device. The data memory control device and the delay memory control device write and read the audio signal data into and from the data memory through data buses independent from each other.

公开(公告)号：US5142489A

公开(公告)日：1992-08-25

申请号：US636457

申请日：1990-12-31

申请人： Makio Yamaki

发明人： Makio Yamaki

IPC分类号： G06F9/38

CPC分类号： G06F9/3842

摘要： A digital signal processor (DSP) makes a conditional judgment based on a value held in a flag register in accordance with the result of an arithmetic operation, selectively outputs data representing either a predetermined value or "0" in accordance with the result of the decision, adds the value of the output data to a value held in a coefficient memory address register, and holds the resultant value in the address register. Accordingly, in executing pipeline processing, a read address of the coefficient data memory can be directly designated without altering the flow of a program, thus shortening the processing speed and facilitating the programming.

摘要翻译： 数字信号处理器（DSP）根据算术结果的结果，根据保存在标志寄存器中的值进行条件判断，根据判定结果有选择地输出表示规定值或“0”的数据 将输出数据的值相加到系数存储器地址寄存器中保存的值，并将结果值保存在地址寄存器中。 因此，在执行流水线处理时，可以直接指定系数数据存储器的读取地址而不改变程序的流程，从而缩短处理速度并便于编程。

公开(公告)号：US5091951A

公开(公告)日：1992-02-25

申请号：US486866

申请日：1990-03-01

申请人： Kazunaga Ida ,  Makio Yamaki ,  Yukio Matsumoto ,  Hiroyuki Ishihara ,  Toshiyuki Naoe ,  Hideyuki Terauchi

发明人： Kazunaga Ida ,  Makio Yamaki ,  Yukio Matsumoto ,  Hiroyuki Ishihara ,  Toshiyuki Naoe ,  Hideyuki Terauchi

IPC分类号： G06F17/10

CPC分类号： G06F17/10

摘要： An audio signal data processing system includes first and second processing devices for processing audio signal data, the first and second processing device having input and output ports of at least two channels, and a control device for controlling the operation of the first and second processing device. The input audio signal data is supplied to the input port of one channel of each of the first and second processing devices, and output data from the output port of said one channel of said first processing device is supplied to the input port of the other channel of the second processing device, and output audio signl data are obtained at each output port of both channels of the second processing device. With this arrangement, one of the cascade processing and the parallel processing can be selectively performed without using a change-over switch provided outside the system.

公开(公告)号：US5065433A

公开(公告)日：1991-11-12

申请号：US476949

申请日：1990-02-08

申请人： Kazunaga Ida ,  Tatsushi Iizuka ,  Makio Yamaki ,  Hiroyuki Ishihara ,  Yukio Matsumoto ,  Kazuhiro Hayashi

发明人： Kazunaga Ida ,  Tatsushi Iizuka ,  Makio Yamaki ,  Hiroyuki Ishihara ,  Yukio Matsumoto ,  Kazuhiro Hayashi

IPC分类号： G06F17/10

CPC分类号： G06F17/10 ,  Y10S84/26

摘要： An audio signal data processing system comprises an input device sequentially supplying incoming audio signal data, a data memory control device writing and reading-out the audio signal data into and from a data memory, a delay memory control device sequentially reading-out the audio signal data from the data memory and storing the data into a delay memory and sequentially reading-out the audio signal data from the delay memory and writing the data into the data memory, an arithmetic device multiplying predetermined coefficient data by the audio signal data having been read-out by the delay memory control device and written into the data memory and summing up results of the multiplication. The arithmetic device includes a plurality of multiplication and summing devices multiplying coefficient data by the audio signal data for each of data groups which are obtained by grouping a predetermined number of the audio signal data read-out by the reading device sequentially in the order of reading and subsequently summing up the multiplied values, and a filter device for executing a filter characteristic operation for calculated values respectively obtained by each of the multiplying and summing device, wherein a filter characteristic of the filtering device is made adjustable.

公开(公告)号：US5331582A

公开(公告)日：1994-07-19

申请号：US990168

申请日：1992-12-14

申请人： Shuhei Sudo ,  Makio Yamaki

发明人： Shuhei Sudo ,  Makio Yamaki

IPC分类号： G06F7/556 ,  G06F1/02

CPC分类号： G06F7/556

摘要： A digital signal processor (DSP) computes logarithmic values for data values of the input signal by using an approximation formula expanded into power series. To reduce the number of computing steps, the processor includes a shift circuit for shifting an input data value into a predetermined range of numeric values, a high-order coefficient memory for storing coefficient values of high order coefficients other than a zero-order coefficient of the approximation formula for data values within the predetermined range of numeric values, a zero-order coefficient memory for storing a coefficient value of the zero-order coefficient shifted according to the number of digits shifted by the shift circuit, and an address specifying circuit for specifying a reading address of the zero-order memory corresponding to the number of digit shifted by the shifted circuit. Also, a DSP computes an inverse logarithmic value of a data value of the input signal by using an approximation formula expanded into power series. The processor includes a summing circuit for summing a specific value to an input data value so that a summed value falls within a predetermined range of numeric values, a coefficient memory for storing coefficient values of the approximation formula for data values within the predetermined range of numeric values, and a shift circuit for shifting a result of computation performed by using the approximation formula by a number of digits corresponding to the specific value summed by the summing circuit.

摘要翻译： 数字信号处理器（DSP）通过使用扩展为幂级数的近似公式来计算输入信号的数据值的对数值。 为了减少计算步骤的数量，处理器包括用于将输入数据值移位到预定数值范围的移位电路，用于存储除零序系数以外的高次系数的系数值的高阶系数存储器 在数值的预定范围内的数据值的近似公式，用于存储根据由移位电路偏移的位数移位的零级系数的系数值的零级系数存储器，以及用于 指定对应于由移位电路移位的数字数量的零级存储器的读取地址。 此外，DSP通过使用扩展为幂级数的近似公式来计算输入信号的数据值的对数值。 该处理器包括：求和电路，用于将特定值与输入数据值进行求和，使得相加的值落在预定的数值范围内;系数存储器，用于存储数字值的数学值的系数值，该数据值在预定数值范围内 值和移位电路，用于将通过使用近似公式执行的计算结果移位与由求和电路相加的特定值相对应的位数。

公开(公告)号：US5255323A

公开(公告)日：1993-10-19

申请号：US880302

申请日：1992-05-05

申请人： Hiroyuki Ishihara ,  Kazunaga Ida ,  Kazuo Watanabe ,  Soichi Toyama ,  Makio Yamaki

发明人： Hiroyuki Ishihara ,  Kazunaga Ida ,  Kazuo Watanabe ,  Soichi Toyama ,  Makio Yamaki

IPC分类号： G01R23/16 ,  H03G3/00 ,  H03G5/00

CPC分类号： G01R23/16 ,  H03G3/002 ,  H03G5/005

摘要： A digital signal processing device for outputting a holding data in an output register from a DSP in synchronism with a second clock pulse having a frequency lower than that of a first clock pulse for conducting arithmetic processing in the DSP. Accordingly, data to be output from the DSP can be directly read by a microcomputer, and contents in a coefficient memory and a delay time memory, for example, can be updated in accordance with the read data. Further, the digital signal processing device can be applied to an audio apparatus such as a loudness controller and a spectrum indicating apparatus.

摘要翻译： 一种数字信号处理装置，用于与具有低于第一时钟脉冲的频率的第二时钟脉冲同步地从DSP输出输出寄存器中的保持数据，以进行DSP中的算术处理。 因此，可以由微处理器直接读取从DSP输出的数据，例如可以根据读取的数据更新系数存储器和延迟时间存储器中的内容。 此外，数字信号处理装置可以应用于诸如响度控制器和频谱指示装置的音频装置。