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    Buck Converter Power Package
    1.
    发明申请
    Buck Converter Power Package 有权
    降压转换器电源包

    公开(公告)号：US20140118032A1

    公开(公告)日：2014-05-01

    申请号：US13666854

    申请日：2012-11-01

    Applicant: Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

    Inventor： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

    IPC: H02M3/155

    CPC classification number: H01L25/18 ,  H01L25/072 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/16251 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00

    Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

    Abstract translation: 一个示例性的公开的实施例包括包括垂直导通控制晶体管和垂直导通同步晶体管的半导体封装。 垂直传导控制晶体管可以包括控制源，控制栅极和控制漏极，其都可从底表面接近，从而使电和直接表面安装到支撑表面。 垂直导通同步晶体管可以包括顶表面上的同步漏极，其可连接到耦合到支撑表面的导电夹子。 导电夹子也可以热耦合到控制晶体管。 因此，晶体管的所有端子容易通过支撑表面接近，并且诸如降压转换器电源相的功率电路可以通过支撑表面的迹线来实现。 可选地，驱动器IC可以集成到封装中，并且散热器可以附接到导电夹子。

    Method and system for parallel processing of IC design layouts
    2.
    发明授权
    Method and system for parallel processing of IC design layouts 有权
    IC设计布局并行处理方法与系统

    公开(公告)号：US08448096B1

    公开(公告)日：2013-05-21

    申请号：US11479600

    申请日：2006-06-30

    Applicant: Xiaojun Wang ,  Roland Ruehl ,  Li-Ling Ma ,  Mathew Koshy ,  Tianhao Zhang ,  Udayan Gumaste ,  Krzysztof Antoni Kozminski ,  Haifang Liao ,  Xinming Tu ,  Xu Zhu

    Inventor： Xiaojun Wang ,  Roland Ruehl ,  Li-Ling Ma ,  Mathew Koshy ,  Tianhao Zhang ,  Udayan Gumaste ,  Krzysztof Antoni Kozminski ,  Haifang Liao ,  Xinming Tu ,  Xu Zhu

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/04

    Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

    Abstract translation: 公开了一种用于并行处理由IC布局处理工具执行的任务的方法和系统。 在一些方法中，IC布局被划分为多个布局部分，并且一个或多个布局部分被并行处理，其中进行几何选择操作，其中用于不同布局部分的数据可以在不同处理实体之间共享。 一种方法包括以下操作：选择在布局部分内执行初始选择动作的第一阶段操作; 分布式区域划分行动; 全局分区和二进制选择的分布式分区动作; 对于基于计数的选择操作的计数选择聚合; 并选择第二阶段操作来组合内部形状和界面形状的选择结果。

    MATRIX VIEW OF ITEMS
    4.
    发明申请
    MATRIX VIEW OF ITEMS 审中-公开
    MATRIX查看项目

    公开(公告)号：US20110161354A1

    公开(公告)日：2011-06-30

    申请号：US12937664

    申请日：2008-04-25

    Applicant: Ling Ma

    Inventor： Ling Ma

    IPC: G06F17/30 ,  G06F3/048

    CPC classification number: G06F16/9038

    Abstract: Apparatus, systems, and methods may operate to present a plurality of searched items by a plurality of points in a matrix view, which includes a first axis and a second axis, respectively representing a price attribute and one of other attributes of the plurality of items. Additional apparatus, systems, and methods are disclosed.

    Abstract translation: 装置，系统和方法可以操作以通过矩阵视图中的多个点呈现多个搜索项目，该矩阵视图包括分别表示价格属性和多个项目的其他属性之一的第一轴和第二轴 。 公开了附加装置，系统和方法。

    MULTI-TOUCH TOUCHSCREEN INCORPORATING PEN TRACKING
    7.
    发明申请
    MULTI-TOUCH TOUCHSCREEN INCORPORATING PEN TRACKING 有权
    多触摸触控笔记录笔记本

    公开(公告)号：US20100001963A1

    公开(公告)日：2010-01-07

    申请号：US12168688

    申请日：2008-07-07

    Applicant: Bernard Doray ,  Paul To ,  Michael Haller ,  James Robert Powell ,  Peter Brandl ,  Jakob Leitner ,  Thomas Josef Seifried ,  Moses Tao-Ling Ma

    Inventor： Bernard Doray ,  Paul To ,  Michael Haller ,  James Robert Powell ,  Peter Brandl ,  Jakob Leitner ,  Thomas Josef Seifried ,  Moses Tao-Ling Ma

    IPC: G06F3/041

    CPC classification number: G06F3/03545 ,  G06F3/0421 ,  G06F3/04883 ,  G06F2203/04109 ,  G06F2203/04808

    Abstract: The present invention relates to a multi-touch display system that supports both multi-touch human input as well as input from a digital pen. The display system has a display panel that is configured to allow human touches along a front surface to be detected and tracked. The display panel also includes a location pattern that preferably covers the viewable areas of the display panel. The location pattern is configured to allow any location within the location pattern to be detected by analyzing a portion of the display pattern that is associated with the particular location. The digital pen is used to “write” on the display panel, wherein such a writing function involves detecting the location where writing occurs and controlling display content that is displayed on the display panel to reflect what is being written.

    Abstract translation: 本发明涉及一种多触摸显示系统，其支持多点触摸人输入以及数字笔的输入​​。 显示系统具有显示面板，其被配置为允许检测和跟踪沿前表面的人体触摸。 显示面板还包括优选地覆盖显示面板的可视区域的位置图案。 位置图案被配置为通过分析与特定位置相关联的显示图案的一部分来允许检测位置图案内的任何位置。 数字笔用于在显示面板上“写入”，其中这种写入功能涉及检测写入的位置，并控制显示在显示面板上的显示内容以反映正在被写入的内容。

    Slider having adjusted transducer recession and method of adjusting recession
    9.
    发明授权
    Slider having adjusted transducer recession and method of adjusting recession 有权
    调整传感器衰退的滑块和调整衰退的方法

    公开(公告)号：US07212381B2

    公开(公告)日：2007-05-01

    申请号：US10641282

    申请日：2003-08-14

    Applicant: Youping Mei ,  Jun Mou ,  Dale E. Egbert ,  Ling Ma

    Inventor： Youping Mei ,  Jun Mou ,  Dale E. Egbert ,  Ling Ma

    IPC: G11B5/56 ,  G11B5/60

    CPC classification number: G11B5/3136 ,  G11B5/102 ,  G11B5/40 ,  G11B5/455 ,  G11B5/607 ,  Y10T29/49021 ,  Y10T29/49025 ,  Y10T29/49032 ,  Y10T29/49041 ,  Y10T29/49798

    Abstract: A method and apparatus are provided for adjusting recession of an element, such as a pole tip, in a transducer structure formed in a plurality of thin film layers on an edge of a slider. A pre-stressed structure is formed as part of the plurality of thin film layers on the edge of the slider. The pre-stressed structure has a level of material stress. The recession is measured relative to a bearing surface of the slider, and then the level of material stress is adjusted as a function of the measured to effect a corresponding change in the recession.

    Abstract translation: 提供一种方法和装置，用于调节在滑块的边缘上形成在多个薄膜层中的换能器结构中的元件（例如极尖）的凹陷。 在滑块的边缘上形成预应力结构作为多个薄膜层的一部分。 预应力结构具有材料应力水平。 相对于滑块的支承表面测量凹陷，然后根据所测量的材料应力的水平来调节以实现经济衰退的相应变化。

    Flip chip semiconductor device and process of its manufacture
    10.
    发明申请
    Flip chip semiconductor device and process of its manufacture 有权
    倒装芯片半导体器件及其制造工艺

    公开(公告)号：US20070063316A1

    公开(公告)日：2007-03-22

    申请号：US11524178

    申请日：2006-09-20

    Applicant: Ling Ma

    Inventor： Ling Ma

    IPC: H01L29/40

    CPC classification number: H01L29/7809 ,  H01L21/76898 ,  H01L29/0653 ,  H01L29/41741 ,  H01L29/41766 ,  H01L2224/81801 ,  H01L2924/13091

    Abstract: A semiconductor die and method of making it are provided. The die includes a first via extending through the entire thickness of the die and a first via electrode disposed inside the via electrically connecting an electrode at a top surface of the die with another electrode disposed at a bottom surface of the die.

    Abstract translation: 提供半导体管芯及其制造方法。 芯片包括延伸穿过芯片的整个厚度的第一通孔和布置在通孔内部的第一通孔电极，电极将模具的顶表面处的电极与设置在管芯的底表面处的另一个电极连接。

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