公开(公告)号：US07589376B2

公开(公告)日：2009-09-15

申请号：US12199307

申请日：2008-08-27

申请人： Jae-Hwang Kim ,  Seung-Beom Yoon ,  Kwang-Wook Koh ,  Chang-Hun Lee ,  Sung-Ho Kim ,  Sung-Chul Park ,  Ju-Ri Kim

发明人： Jae-Hwang Kim ,  Seung-Beom Yoon ,  Kwang-Wook Koh ,  Chang-Hun Lee ,  Sung-Ho Kim ,  Sung-Chul Park ,  Ju-Ri Kim

IPC分类号： H01L29/94

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

摘要翻译： EEPROM器件包括设置在半导体衬底的预定区域以限定有源区的器件隔离层，与器件隔离层交叉的一对控制栅极和有源区，插入控制栅极之间的一对选择栅极， 器件隔离层和有源区以及顺序地堆叠在控制栅极和有源区之间的浮置栅极和隔间栅极电介质图案。EEPROM器件还包括插入浮置栅极和有源区域之间的存储晶体管的栅极绝缘层，以及 隧道绝缘层比存储晶体管的栅极绝缘层薄，并且选择晶体管的栅极绝缘层插入在选择栅极和有源区之间。 隧道绝缘层在与浮动栅极相邻的一侧对准。

公开(公告)号：US20080266981A1

公开(公告)日：2008-10-30

申请号：US12173742

申请日：2008-07-15

申请人： KWANG WOOK KOH ,  Jeong-Uk Han

发明人： KWANG WOOK KOH ,  Jeong-Uk Han

IPC分类号： G11C11/34 ,  H01L29/788

CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7885

摘要： A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region, and first and second select gates formed on the channel regions and opposite sidewalls of the stacked gate structure. Since the first and second select gates are spacer-shaped to be self-aligned on opposite sidewalls of the stacked gate structure, a size of a memory cell is reduced to enhance an integration density of a semiconductor device.

摘要翻译： 非易失性存储器件包括形成在半导体衬底中的第一和第二杂质扩散区，以及形成在第一和第二杂质扩散区之间的半导体衬底的沟道区上的存储单元。 存储单元包括形成在沟道区上的堆叠栅极结构，以及形成在堆叠栅极结构的沟道区和相对侧壁上的第一和第二选择栅。 由于第一选择栅极和第二选择栅极是间隔形状以在层叠栅极结构的相对侧壁上自对准，所以减小了存储单元的尺寸以增强半导体器件的集成密度。

公开(公告)号：US07371640B2

公开(公告)日：2008-05-13

申请号：US11378505

申请日：2006-03-17

申请人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

发明人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

摘要翻译： 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 顺序地形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层组成的三层。 然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US20070194369A1

公开(公告)日：2007-08-23

申请号：US11704003

申请日：2007-02-08

申请人： Kwang-Wook Koh ,  Hee-Seog Jeon

发明人： Kwang-Wook Koh ,  Hee-Seog Jeon

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L27/11524 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521

摘要： In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

摘要翻译： 在非易失性存储器件及其制造方法中，形成在半导体衬底中限定有源区的器件隔离层。 在半导体衬底上形成栅绝缘层和第一导电层。 形成一对堆叠图案，每一个在第一导电层上具有隔间电介质层图案和第二导电层图案。 在堆叠图案之间的第一导电层图案上形成掩模图案，掩模图案与每个堆叠图案间隔开。 使用堆叠图案和掩模图案作为蚀刻掩模来图案化第一导电层。 将杂质离子注入到有源区中以形成一对非易失性存储晶体管和选择晶体管。 所得到的非易失性存储器件包括包括一对非易失性存储晶体管和选择晶体管的存储单元单元。

公开(公告)号：US20070023820A1

公开(公告)日：2007-02-01

申请号：US11488983

申请日：2006-07-19

申请人： Seung-Jin Yang ,  Jeong-Uk Han ,  Kwang-Wook Koh ,  Jae-Hwang Kim ,  Sung-Chul Park ,  Ju-Ri Kim

发明人： Seung-Jin Yang ,  Jeong-Uk Han ,  Kwang-Wook Koh ,  Jae-Hwang Kim ,  Sung-Chul Park ,  Ju-Ri Kim

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L29/42328 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883

摘要： In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

摘要翻译： 在非易失性存储器件及其形成和操作它的方法中，当浮置栅极和控制栅极堆叠时，一个存储器晶体管包括覆盖浮置栅极的两个侧壁的侧壁选择栅极。 侧壁选择门是间隔件形式。 由于侧壁选择栅极在浮动栅极的侧壁上是间隔物形式，所以可以提高电池的集成度。 此外，由于侧壁选择栅极设置在浮置栅极的两个侧壁上，所以可以控制从位线和公共源极线施加的电压，因此可以防止常规的写入/擦除错误。 因此，可以提高阈值电压的分布。

公开(公告)号：US20060071265A1

公开(公告)日：2006-04-06

申请号：US11232284

申请日：2005-09-21

申请人： Kwang-Wook Koh ,  Jeong-Uk Han

发明人： Kwang-Wook Koh ,  Jeong-Uk Han

IPC分类号： H01L21/8238 ,  H01L29/788

CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7885

摘要： A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region, and first and second select gates formed on the channel regions and opposite sidewalls of the stacked gate structure. Since the first and second select gates are spacer-shaped to be self-aligned on opposite sidewalls of the stacked gate structure, a size of a memory cell is reduced to enhance an integration density of a semiconductor device.

摘要翻译： 非易失性存储器件包括形成在半导体衬底中的第一和第二杂质扩散区，以及形成在第一和第二杂质扩散区之间的半导体衬底的沟道区上的存储单元。 存储单元包括形成在沟道区上的堆叠栅极结构，以及形成在堆叠栅极结构的沟道区和相对侧壁上的第一和第二选择栅。 由于第一选择栅极和第二选择栅极是间隔形状以在层叠栅极结构的相对侧壁上自对准，所以减小了存储单元的尺寸以增强半导体器件的集成密度。

公开(公告)号：US06815764B2

公开(公告)日：2004-11-09

申请号：US10388631

申请日：2003-03-17

申请人： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

发明人： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

IPC分类号： H01L29792

CPC分类号： H01L29/792 ,  H01L29/7923 ,  Y10S438/954

摘要： A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

摘要翻译： 具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。 第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。 相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

公开(公告)号：US07799635B2

公开(公告)日：2010-09-21

申请号：US12476698

申请日：2009-06-02

申请人： Kwang-Wook Koh ,  Hee-Seog Jeon

发明人： Kwang-Wook Koh ,  Hee-Seog Jeon

IPC分类号： H01L21/336 ,  H01L21/8239

CPC分类号： H01L27/11524 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521

摘要： In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

摘要翻译： 在非易失性存储器件及其制造方法中，形成在半导体衬底中限定有源区的器件隔离层。 在半导体衬底上形成栅绝缘层和第一导电层。 形成一对堆叠图案，每一个在第一导电层上具有隔间电介质层图案和第二导电层图案。 在堆叠图案之间的第一导电层图案上形成掩模图案，掩模图案与每个堆叠图案间隔开。 使用堆叠图案和掩模图案作为蚀刻掩模来图案化第一导电层。 将杂质离子注入到有源区中以形成一对非易失性存储晶体管和选择晶体管。 所得到的非易失性存储器件包括包括一对非易失性存储晶体管和选择晶体管的存储单元单元。

公开(公告)号：US07170794B2

公开(公告)日：2007-01-30

申请号：US10971201

申请日：2004-10-21

申请人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

发明人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

IPC分类号： G11C11/34

CPC分类号： G11C16/0425

摘要： A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

摘要翻译： 非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。 非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。 电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。 通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。

公开(公告)号：US20060157775A1

公开(公告)日：2006-07-20

申请号：US11378295

申请日：2006-03-20

申请人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

发明人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.