公开(公告)号：US08597081B2

公开(公告)日：2013-12-03

申请号：US13241421

申请日：2011-09-23

Applicant: Jae-Kwang Choi ,  Hong-Jin Kim ,  Keon-Sik Seo ,  Sol Han ,  Kun-Tack Lee ,  Byoung-Ho Kwon

Inventor： Jae-Kwang Choi ,  Hong-Jin Kim ,  Keon-Sik Seo ,  Sol Han ,  Kun-Tack Lee ,  Byoung-Ho Kwon

IPC: B24B1/00

CPC classification number: B24B53/017

Abstract: A pad conditioning disk, a pre-conditioning unit, and a CMP apparatus having the same are provided. The pad conditioning disk includes a base in which mountain-type tips and valley-type grooves are repeatedly connected to each other, and a cutting layer formed on the base layer. The cutting layer including conditioning particles deposited on surfaces of the tips and grooves. A surfaces roughness of conditioning particles deposited on the surfaces of the tips is less than a surface roughness of conditioning particles deposited on the surfaces of the grooves.

Abstract translation: 提供了衬垫调节盘，预调节单元和具有该调节盘的CMP设备。 垫调节盘包括其中山型尖端和谷型沟槽彼此重复连接的基底和形成在基底层上的切割层。 切割层包括沉积在尖端和凹槽表面上的调节颗粒。 沉积在尖端表面上的调理颗粒的表面粗糙度小于沉积在凹槽表面上的调理颗粒的表面粗糙度。

公开(公告)号：US08110499B2

公开(公告)日：2012-02-07

申请号：US12437390

申请日：2009-05-07

Applicant: Dae-Hyuk Kang ,  Young-Hoo Kim ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Jae-Dong Lee ,  Dae-Hong Eom ,  Jeong-Nam Han

Inventor： Dae-Hyuk Kang ,  Young-Hoo Kim ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Jae-Dong Lee ,  Dae-Hong Eom ,  Jeong-Nam Han

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/485 ,  H01L27/24 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.

Abstract translation: 可以在具有接触区域的物体上形成绝缘层。 绝缘层可以被部分蚀刻以形成暴露接触区域的开口。 可以在暴露的接触区域上形成包括硅和氧的材料层。 可以在包括硅和氧的材料层上形成金属层。 包括硅和氧的材料层可以与金属层反应，以至少在接触区域上形成金属氧化物硅化物层。 可以在金属氧化物硅化物层上形成导电层以填充开口。

公开(公告)号：US08084367B2

公开(公告)日：2011-12-27

申请号：US11752834

申请日：2007-05-23

Applicant: Hyo-san Lee ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Jeong-Nam Han ,  Jung-Min Oh ,  Kwon-Taek Lim ,  Ha-Soo Hwang ,  Haldorai Yuvaraj ,  Jae-Mok Jung

Inventor： Hyo-san Lee ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Jeong-Nam Han ,  Jung-Min Oh ,  Kwon-Taek Lim ,  Ha-Soo Hwang ,  Haldorai Yuvaraj ,  Jae-Mok Jung

IPC: H01L21/302

CPC classification number: H01L21/02101 ,  H01L21/31111 ,  H01L21/67051 ,  H01L21/6708 ,  H01L27/10852 ,  Y10S134/902

Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.

Abstract translation: 本文提供了使用超临界流体的蚀刻，清洁和干燥方法以及用于进行该临界流体的室系统。 蚀刻方法包括使用其中溶解蚀刻剂的超临界二氧化碳蚀刻材料层，以及使用超临界二氧化碳除去由材料层和蚀刻化学品之间的反应产生的蚀刻副产物，其中清洁化学品 溶解 还提供了制造半导体器件的方法。

公开(公告)号：US20110306197A1

公开(公告)日：2011-12-15

申请号：US13156729

申请日：2011-06-09

Applicant: Young-Hoo Kim ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Im-Soo Park

Inventor： Young-Hoo Kim ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Im-Soo Park

IPC: H01L21/3205

CPC classification number: H01L28/82

Abstract: Method of manufacturing semiconductor device are provided including forming an insulation layer having a pad on a substrate; forming an etch stop layer on the insulation layer and the pad; forming a mold structure having at least one mold layer on the etch stop layer; forming a first supporting layer on the mold structure; etching the first supporting layer and the mold structure to form a first opening exposing the etch stop layer; forming a spacer on a sidewall of the first opening; etching the etch stop layer using the spacer as an etching mask to form a second opening, different from the first opening, exposing a first portion of the pad having a first associated area; etching the etch stop layer using the spacer as an etching mask to form a third opening exposing a second portion of the pad having a second associated area, the second associated area being larger than the first associated area; and etching the mold structure to form a fourth opening having a width larger than a width of the third opening.

Abstract translation: 提供制造半导体器件的方法，包括在衬底上形成具有衬垫的绝缘层; 在所述绝缘层和所述焊盘上形成蚀刻停止层; 形成在所述蚀刻停止层上具有至少一个模制层的模具结构; 在模具结构上形成第一支撑层; 蚀刻第一支撑层和模具结构以形成暴露蚀刻停止层的第一开口; 在所述第一开口的侧壁上形成间隔件; 使用所述间隔物作为蚀刻掩模来蚀刻所述蚀刻停止层，以形成不同于所述第一开口的第二开口，暴露所述焊盘的具有第一相关区域的第一部分; 使用所述间隔物作为蚀刻掩模来蚀刻所述蚀刻停止层，以形成暴露所述焊盘的具有第二相关区域的第二部分的第三开口，所述第二相关区域大于所述第一相关区域; 并且蚀刻所述模具结构以形成宽度大于所述第三开口的宽度的第四开口。

公开(公告)号：US20110287625A1

公开(公告)日：2011-11-24

申请号：US13079202

申请日：2011-04-04

Applicant: Dae-Hyuk Kang ,  Kun-Tack Lee ,  Dae-Hong Eom ,  Bo-Un Yoon ,  Jeong-Nam Han

Inventor： Dae-Hyuk Kang ,  Kun-Tack Lee ,  Dae-Hong Eom ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC: H01L21/336

CPC classification number: H01L21/28123 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11524 ,  H01L29/40114

Abstract: A method of forming a pattern in a semiconductor device includes forming an etching object layer on a substrate, the etching object layer is an oxide that is substantially free of impurities. A mask is formed on the etching object layer, the mask is an oxide that includes impurities. The etching object layer is patterned using the mask as an etching mask and then the mask is removed. The mask is removed using an etchant having an etching selectivity to an oxide that is substantially free of impurities and an oxide that includes impurities during removing of the mask to limit damage to the patterned etching object layer during removal of the mask.

Abstract translation: 在半导体器件中形成图案的方法包括在基板上形成蚀刻对象层，蚀刻对象层是基本上不含杂质的氧化物。 在蚀刻对象层上形成掩模，掩模是包含杂质的氧化物。 使用掩模将蚀刻对象层图案化为蚀刻掩模，然后去除掩模。 使用具有对基本上不含杂质的氧化物的蚀刻选择性的蚀刻剂去除掩模，以及在除去掩模期间包括杂质的氧化物，以限制在去除掩模期间对图案化的蚀刻对象层的损伤。

公开(公告)号：US07825030B2

公开(公告)日：2010-11-02

申请号：US12277332

申请日：2008-11-25

Applicant: Yu-Kyung Kim ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Chang-Ki Hong

Inventor： Yu-Kyung Kim ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Chang-Ki Hong

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/30617 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/6653

Abstract: A sacrificial layer and wet etch are used to form a sidewall spacer so as to prevent damage to the structure on which the spacer is formed and to the underlying substrate as well. Once the structure is formed on the substrate a spacer formation layer is formed to cover the structure, and a sacrificial layer is formed on the spacer formation layer. The sacrificial layer is wet etched to form a sacrificial layer pattern on that portion of the spacer formation layer extending along a sidewall of the structure. The spacer is formed on the sidewall of the structure by wet etching the spacer formation layer using the sacrificial layer pattern as a mask.

Abstract translation: 使用牺牲层和湿蚀刻来形成侧壁间隔物，以便防止对形成间隔物的结构和下面的衬底造成损坏。 一旦在衬底上形成结构，形成间隔物形成层以覆盖该结构，并且在间隔物形成层上形成牺牲层。 对牺牲层进行湿式蚀刻以在沿着结构的侧壁延伸的间隔物形成层的该部分上形成牺牲层图案。 通过使用牺牲层图案作为掩模湿蚀刻间隔物形成层，在该结构的侧壁上形成间隔物。

公开(公告)号：US07704828B2

公开(公告)日：2010-04-27

申请号：US11741639

申请日：2007-04-27

Applicant: Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Sung-Il Cho

Inventor： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Sung-Il Cho

IPC: H01L21/8242

CPC classification number: H01L28/91

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a mold for forming a storage electrode, forming sacrificial spacers at side walls of openings in the mold, forming a conductive film for a storage electrode along the inside of the openings, removing the mold by a wet etching process, removing the sacrificial spacers by a dry etching process, and sequentially forming a dielectric film and an upper electrode on the storage electrode.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括形成用于形成存储电极的模具，在模具的开口的侧壁处形成牺牲隔离物，沿着开口的内部形成用于存储电极的导电膜，通过湿法蚀刻工艺移除模具， 牺牲隔离物，并且在存储电极上依次形成电介质膜和上电极。

公开(公告)号：US20090117499A1

公开(公告)日：2009-05-07

申请号：US12232594

申请日：2008-09-19

Applicant: Se-yeon Kim ,  Yong-kyun Ko ,  Sang-mi Lee ,  Yang-koo Lee ,  Hun-jung Yi ,  Kun-tack Lee

Inventor： Se-yeon Kim ,  Yong-kyun Ko ,  Sang-mi Lee ,  Yang-koo Lee ,  Hun-jung Yi ,  Kun-tack Lee

IPC: G03F7/20 ,  C11D3/20

CPC classification number: G03F7/70925 ,  G03F7/70341

Abstract: A cleaning solution for an immersion photolithography system according to example embodiments may include an ether-based solvent, an alcohol-based solvent, and a semi-aqueous-based solvent. In the immersion photolithography system, a plurality of wafers coated with photoresist films may be exposed pursuant to an immersion photolithography process using an immersion fluid. The area contacted by the immersion fluid during the exposure process may accumulate contaminants. Accordingly, the area contacted by the immersion fluid during the exposure process may be washed with the cleaning solution according to example embodiments so as to reduce or prevent defects in the immersion photolithography system.

Abstract translation: 根据示例性实施方式的用于浸没式光刻系统的清洁溶液可以包括醚类溶剂，醇类溶剂和半水性溶剂。 在浸没式光刻系统中，可以使用浸没流体根据浸没光刻工艺来曝光涂覆有光致抗蚀剂膜的多个晶片。 在曝光过程中浸入液接触的区域可能会积聚污染物。 因此，可以利用根据示例性实施例的清洗溶液洗涤曝光过程中浸入液接触的区域，以便减少或防止浸没光刻系统中的缺陷。

公开(公告)号：US07498217B2

公开(公告)日：2009-03-03

申请号：US11746761

申请日：2007-05-10

Applicant: Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Woo-Gwan Shim ,  Jong-Won Lee

Inventor： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Woo-Gwan Shim ,  Jong-Won Lee

IPC: H01L21/8238 ,  H01L21/8242 ,  H01L21/336

CPC classification number: H01L27/115 ,  H01L21/76229 ,  H01L27/11568

Abstract: In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.

Abstract translation: 在制造诸如SONOS型半导体器件的半导体器件的方法中，在衬底上形成沟槽。 形成从衬底突出的隔离层以填充沟槽。 在基板上形成第一层之后，在第一层上形成预备的第二层图案。 预备的第二层图案具有基本上低于或基本上等于隔离层的上表面的上表面。 在初步第二层和隔离层上形成第三层。 在第三层上形成第四层。 部分蚀刻第四层，第三层，初步第二层图案和第一层，以在基板上形成栅极结构。 源极/漏极区域形成在与栅极结构相邻的衬底的部分处。

公开(公告)号：US07488688B2

公开(公告)日：2009-02-10

申请号：US10997902

申请日：2004-11-29

Applicant: Seung-pil Chung ,  Kyu-whan Chang ,  Sun-jung Lee ,  Kun-tack Lee ,  Im-soo Park ,  Kwang-wook Lee ,  Moon-hee Lee

Inventor： Seung-pil Chung ,  Kyu-whan Chang ,  Sun-jung Lee ,  Kun-tack Lee ,  Im-soo Park ,  Kwang-wook Lee ,  Moon-hee Lee

IPC: H01L21/302

CPC classification number: H01L21/02057 ,  H01L21/31116

Abstract: A method for removing an oxide layer such as a natural oxide layer and a semiconductor manufacturing apparatus which uses the method to remove the oxide layer. A vertically movable susceptor is installed at the lower portion in a processing chamber and a silicon wafer is loaded onto the susceptor when it is at the lower portion of the processing chamber. The air is exhausted from the processing chamber to form a vacuum condition therein. A hydrogen gas in a plasma state and a fluorine-containing gas are supplied into the processing chamber to induce a chemical reaction with the oxide layer on the silicon wafer, resulting in a reaction layer. Then, the susceptor is moved up to the upper portion of the processing chamber, to anneal the silicon wafer on the susceptor with a heater installed at the upper portion of the processing chamber, thus vaporizing the reaction layer. The vaporized reaction layer is exhausted out of the chamber. The oxide layer can be removed with a high selectivity while avoiding damage or contamination of the underlying layer.

Abstract translation: 用于除去氧化物层的方法，例如天然氧化物层和使用该方法去除氧化物层的半导体制造装置。 垂直移动的基座安装在处理室的下部处，并且当硅晶片位于处理室的下部时，将硅晶片装载到基座上。 空气从处理室排出，在其中形成真空条件。 将等离子体状态的氢气和含氟气体供给到处理室，以引起与硅晶片上的氧化物层的化学反应，产生反应层。 然后，将基座向上移动到处理室的上部，通过安装在处理室上部的加热器对基座上的硅晶片退火，从而使反应层蒸发。 蒸发的反应层被排出室外。 可以以高选择性去除氧化物层，同时避免下层的损坏或污染。