公开(公告)号：US06690598B2

公开(公告)日：2004-02-10

申请号：US09895205

申请日：2001-07-02

Applicant: Koichi Oguchi ,  Eiji Natori ,  Kazumasa Hasegawa

Inventor： Koichi Oguchi ,  Eiji Natori ,  Kazumasa Hasegawa

IPC: G11C1122

CPC classification number: G11C11/22 ,  H01L2924/15153

Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.

Abstract translation: 铁电存储器件包括存储单元阵列和外围电路部分。 其中存储单元以矩阵形式布置的存储单元阵列包括第一信号电极，沿与第一信号电极相交的方向布置的第二信号电极，以及至少设置在第一信号电极之间的交叉区域处的铁电层 第一信号电极和第二信号电极。 外围电路部分包括用于选择性地允许将信息写入或从诸如第一驱动电路，第二驱动电路和信号检测电路的存储单元读取的电路。 存储单元阵列和外围电路部分分层设置在不同的层中。 该铁电存储器件可以显着增加存储单元的集成度并减小芯片面积。

公开(公告)号：US06617627B2

公开(公告)日：2003-09-09

申请号：US09931915

申请日：2001-08-20

Applicant: Eiji Natori ,  Kazumasa Hasegawa ,  Koichi Oguchi ,  Takao Nishikawa ,  Tatsuya Shimoda

Inventor： Eiji Natori ,  Kazumasa Hasegawa ,  Koichi Oguchi ,  Takao Nishikawa ,  Tatsuya Shimoda

IPC: H01L31062

CPC classification number: H01L28/55 ,  G11C11/22 ,  H01L27/101

Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance or load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.

Abstract translation: 本发明涉及一种存储单元阵列，其能够降低信号电极的寄生电容或负载电容，并且具有构成铁电电容器并具有预定图案的铁电层; 一种制造该存储单元阵列的方法和一种铁电存储器件。 在存储单元阵列中，由铁电电容器形成的存储单元被布置成矩阵。 铁电电容器包括第一信号电极，沿与第一信号电极交叉的方向排列的第二信号电极，以及沿第一信号电极或第二信号电极线性配置的铁电层。 或者，铁电层可以仅设置在第一和第二信号电极的交叉区域中。

公开(公告)号：US06791863B2

公开(公告)日：2004-09-14

申请号：US10715500

申请日：2003-11-19

Applicant: Koichi Oguchi ,  Eiji Natori ,  Kazumasa Hasegawa

Inventor： Koichi Oguchi ,  Eiji Natori ,  Kazumasa Hasegawa

IPC: G11C1122

CPC classification number: G11C11/22 ,  H01L2924/15153

Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.

公开(公告)号：US06727536B2

公开(公告)日：2004-04-27

申请号：US09934550

申请日：2001-08-23

Applicant: Kazumasa Hasegawa ,  Eiji Natori ,  Takao Nishikawa ,  Koichi Oguchi ,  Tatsuya Shimoda

Inventor： Kazumasa Hasegawa ,  Eiji Natori ,  Takao Nishikawa ,  Koichi Oguchi ,  Tatsuya Shimoda

IPC: H01L2976

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.

Abstract translation: 本发明的铁电体存储装置具备存储单元阵列，其中存储单元配置成具有第一信号电极的矩阵，第二信号电极沿与第一信号电极交叉的方向排列，以及至少设置在交叉区域的铁电层 在第一信号电极和第二信号电极之间，以及周边电路部分，用于选择性地将信息写入或从存储器单元读取信息。 存储单元阵列和外围电路部分形成在不同的层中。 外围电路部分形成在存储单元阵列外部的区域中。

公开(公告)号：US4648691A

公开(公告)日：1987-03-10

申请号：US218582

申请日：1980-12-19

Applicant: Koichi Oguchi ,  Minoru Hosokawa ,  Satoru Yazawa ,  Mitsuo Nagata

Inventor： Koichi Oguchi ,  Minoru Hosokawa ,  Satoru Yazawa ,  Mitsuo Nagata

IPC: G02F1/136 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/139 ,  G09F9/30 ,  G02F1/13

CPC classification number: G02F1/133504 ,  G02F1/133553 ,  G02F1/136277 ,  G02F1/13725 ,  G02F2203/02

Abstract: A liquid crystal display device wherein display elements are arranged in a matrix display on a substrate and the display is driven in response to external display signals is provided. The display device includes a thin film layer having a rugged diffusing surface and an opposed transparent electrode plate spaced apart from the thin film layer. A guest-host liquid crystal material including a pleochroic dye is utilized. The thin film layer may be a metal film such as, aluminum, an aluminum alloy, silver or a silver alloy having a rugged surface for providing a diffused white surface formed by vaccum evaporation, sputtering, heat-treatment, recrystallization or etching.

Abstract translation: 一种液晶显示装置，其中显示元件被布置在基板上的矩阵显示器中，并且响应于外部显示信号而驱动显示器。 显示装置包括具有凹凸漫射面的薄膜层和与薄膜层隔开的相对的透明电极板。 使用包含多色染料的客体主体液晶材料。 薄膜层可以是金属膜，例如具有凹凸表面的铝，铝合金，银或银合金，用于提供通过真空蒸发，溅射，热处理，再结晶或蚀刻形成的扩散的白色表面。

公开(公告)号：US06913937B2

公开(公告)日：2005-07-05

申请号：US10618688

申请日：2003-07-15

Applicant: Eiji Natori ,  Kazumasa Hasegawa ,  Koichi Oguchi ,  Takao Nishikawa ,  Tatsuya Shimoda

Inventor： Eiji Natori ,  Kazumasa Hasegawa ,  Koichi Oguchi ,  Takao Nishikawa ,  Tatsuya Shimoda

IPC: H01L27/105 ,  G11C11/22 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/10 ,  H01L21/00

CPC classification number: H01L28/55 ,  G11C11/22 ,  H01L27/101

Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.

Abstract translation: 本发明涉及一种存储单元阵列，其能够降低信号电极的负载电容的寄生电容，并且具有构成铁电电容器并具有预定图案的铁电层; 一种制造该存储单元阵列的方法和一种铁电存储器件。 在存储单元阵列中，由铁电电容器形成的存储单元被布置成矩阵。 铁电电容器包括第一信号电极，沿与第一信号电极交叉的方向排列的第二信号电极，以及沿着第一信号电极或第二信号电极线性配置的铁电体层。 或者，铁电层可以仅设置在第一和第二信号电极的交叉区域中。

公开(公告)号：US4429305A

公开(公告)日：1984-01-31

申请号：US154354

申请日：1980-05-29

Applicant: Minoru Hosokawa ,  Koichi Oguchi ,  Satoru Yazawa

Inventor： Minoru Hosokawa ,  Koichi Oguchi ,  Satoru Yazawa

IPC: G02F1/133 ,  G02F1/136 ,  G02F1/1368 ,  G09G3/36

CPC classification number: G09G3/3648 ,  G09G2300/0876

Abstract: A matrix liquid crystal display circuit includes a selecting transistor connected to the picture element and a capacitor for each picture element of the matrix. The other picture element and capacitor terminals connect to common electrodes and the transistor gates in each row connect to a common electrode. In each column a common source line connects to the sources of the transistors and a signal sampling circuit periodically applies an image signal to the source line of each column in sequence. No amplification is used between the sampling circuit and the transistor sources. Metallic leads serve as the source lines, but other circuits and components are integrated on a common substrate.

Abstract translation: 矩阵液晶显示电路包括连接到像素的选择晶体管和矩阵的每个像素的电容器。 其他像素和电容器端子连接到公共电极，并且每行中的晶体管栅极连接到公共电极。 在每列中，公共源极线连接到晶体管的源极，并且信号采样电路周期性地将图像信号施加到每列的源极线。 在采样电路和晶体管源之间不使用放大。 金属引线用作源极线，但是其它电路和部件集成在公共基板上。

公开(公告)号：US07169621B2

公开(公告)日：2007-01-30

申请号：US10780572

申请日：2004-02-19

Applicant: Kazumasa Hasegawa ,  Eiji Natori ,  Takao Nishikawa ,  Koichi Oguchi ,  Tatsuya Shimoda

Inventor： Kazumasa Hasegawa ,  Eiji Natori ,  Takao Nishikawa ,  Koichi Oguchi ,  Tatsuya Shimoda

IPC: H01L21/00

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.

Abstract translation: 本发明的铁电体存储装置具备存储单元阵列，其中存储单元配置成具有第一信号电极的矩阵，第二信号电极沿与第一信号电极交叉的方向排列，以及至少设置在交叉区域的铁电层 在第一信号电极和第二信号电极之间，以及用于选择性地将信息写入或从存储单元读取信息的外围电路部分。 存储单元阵列和外围电路部分形成在不同的层中。 外围电路部分形成在存储单元阵列外部的区域中。