公开(公告)号：US09162858B2

公开(公告)日：2015-10-20

申请号：US13698461

申请日：2012-03-13

Applicant: Kouji Nishiyama ,  Kazuhiro Kurihara

Inventor： Kouji Nishiyama ,  Kazuhiro Kurihara

IPC: B66F9/06 ,  B66F9/075 ,  B60R16/04 ,  B60S5/06

CPC classification number: B66F9/07572 ,  B60R16/04 ,  B60S5/06 ,  B66F9/0754 ,  B66F9/07545

Abstract: To facilitate loading-unloading operation of a battery even when a large-sized battery is mounted, in a battery-powered forklift which is driven with power of a battery mounted on a vehicle body including a fork which is arranged at a front part of the vehicle body, a counter weight which is arranged at a rear part of the vehicle body, and a top plate which is supported at a position to cover an area above a driver seat via a pair of rear stays 44 extended upward from both sides of the rear part of the vehicle body, post members arranged in a raised manner at both sides of the counter weight guide movement of the battery along the front-rear direction of the vehicle body between the post members.

Abstract translation: 即使在安装大型电池的情况下，为了便于进行电池的卸载操作，在由电池驱动的电动叉车中驱动，该电动车由安装在车身上的电池驱动，该车辆包括叉子， 车体，配置在车身后部的配重，以及顶板，其被支撑在通过从所述车身的两侧向上延伸的一对后撑架44覆盖驾驶员座椅上方的区域的位置 车体的后部，沿着车身前后方向在柱构件之间的电池的配重引导运动的两侧以升高的方式布置的柱构件。

公开(公告)号：US08933849B2

公开(公告)日：2015-01-13

申请号：US13637832

申请日：2011-03-28

Applicant: Kazuhiro Kurihara

Inventor： Kazuhiro Kurihara

IPC: H01Q1/24 ,  H01Q1/38 ,  H01Q9/42 ,  H04M1/02

CPC classification number: H01Q1/243 ,  H01Q1/38 ,  H01Q9/42 ,  H04M1/0235

Abstract: A slide type portable wireless device includes: a first housing; a second housing which slides relative to the first housing, and is positioned at either of a first relative position and a second relative position different from the first relative position; an antenna element which is embedded in the first housing; and a plurality of parasitic elements which are provided in the second housing, and includes first and second parasitic elements capacity coupled with the antenna element. The first parasitic element faces the antenna element at the first relative position. The second parasitic element faces the antenna element at the second relative position.

Abstract translation: 滑盖型便携式无线装置包括：第一壳体; 第二壳体，其相对于第一壳体滑动，并且位于不同于第一相对位置的第一相对位置和第二相对位置中的任一个处; 天线元件，其嵌入在所述第一壳体中; 以及设置在第二壳体中的多个寄生元件，并且包括与天线元件耦合的第一和第二寄生元件。 第一寄生元件在第一相对位置面向天线元件。 第二寄生元件在第二相对位置面对天线元件。

公开(公告)号：US08789636B2

公开(公告)日：2014-07-29

申请号：US13816415

申请日：2012-03-13

Applicant: Kouji Nishiyama ,  Kazuhiro Kurihara ,  Tetsuya Okuyama

Inventor： Kouji Nishiyama ,  Kazuhiro Kurihara ,  Tetsuya Okuyama

IPC: B60R16/04

CPC classification number: B66F9/07572 ,  B60K1/04 ,  B60K2001/0422 ,  B60K2001/0455 ,  B60K2001/0466 ,  B60Y2200/15 ,  B66F9/0754

Abstract: A battery-powered forklift including a fork placed at an anterior portion of a vehicle body, and a counter weight placed at a posterior portion of the vehicle body, the battery-powered forklift running by electric power of a battery mounted on the vehicle body, wherein a concave portion that is open in a longitudinal direction is formed at an upper surface of the counter weight, the battery is mounted on a position above a rear wheel of the vehicle body while at least a part of the battery overlaps with the counter weight, and the battery is removable toward a rear of the vehicle body through the concave portion of the counter weight.

Abstract translation: 一种电池供电的叉车，包括放置在车身前部的叉子，以及放置在车体后部的配重，所述电池供电的叉车由安装在车体上的电池的电力运行， 其特征在于，在所述配重的上表面形成有在长度方向上开口的凹部，所述电池被安装在所述车体的后轮上方的位置，同时所述电池的至少一部分与所述配重重叠 并且电池通过配重的凹部朝向车体的后部移除。

公开(公告)号：US07898879B2

公开(公告)日：2011-03-01

申请号：US12574427

申请日：2009-10-06

Applicant: Hiroaki Wada ,  Kazuhiro Kurihara

Inventor： Hiroaki Wada ,  Kazuhiro Kurihara

IPC: G11C5/14

CPC classification number: G11C16/30 ,  G11C5/147 ,  H04N5/23241

Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

Abstract translation: 本发明是一种半导体器件，包括：串联连接在电源Vcc（第一电源）和地（第二电源）之间的电阻器R11（第一电阻器部分）和FET 15（第二电阻器部件）; 输出节点N11，设置在电阻器R11和FET15之间，用于输出参考电压; 设置在电源Vcc和地之间的反馈节点N12; 以及通过使用输出节点N11的参考电压和反馈节点N12的电压将反馈节点N12的电压维持在恒定电平的电压控制电路（19）。 本发明可以提供一种具有能够产生不依赖于电源电压的参考电压的参考电压产生电路及其控制方法的半导体器件。

公开(公告)号：US07889577B2

公开(公告)日：2011-02-15

申请号：US12491970

申请日：2009-06-25

Applicant: Hiroki Murakami ,  Kazuhiro Kurihara

Inventor： Hiroki Murakami ,  Kazuhiro Kurihara

IPC: G11C7/10

CPC classification number: G11C11/413 ,  G11C16/102 ,  G11C16/105

Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.

Abstract translation: 一种半导体器件包括：具有全部要被擦除并具有闪存单元的数据的第一扇区（12）; 具有全部要保留并具有闪存单元的数据的第二扇区（14）; 扇区选择电路（16）在擦除第一扇区中的数据期间从扇区中选择一对扇区，所述一对扇区是第一扇区和第二扇区; 以及保持第二扇区的数据的SRAM阵列（存储）（30）。 本发明可以提供一种半导体器件，其中使用了减少数量的扇区选择电路，使得可以减小存储单元阵列的面积并提供一种控制半导体器件的方法。

公开(公告)号：US20090300275A1

公开(公告)日：2009-12-03

申请号：US12491970

申请日：2009-06-25

Applicant: Hiroki MURAKAMI ,  Kazuhiro KURIHARA

Inventor： Hiroki MURAKAMI ,  Kazuhiro KURIHARA

IPC: G06F12/02

CPC classification number: G11C11/413 ,  G11C16/102 ,  G11C16/105

Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.

公开(公告)号：US20080117678A1

公开(公告)日：2008-05-22

申请号：US12017693

申请日：2008-01-22

Applicant: Ming-Huei Shieh ,  Kazuhiro Kurihara

Inventor： Ming-Huei Shieh ,  Kazuhiro Kurihara

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2211/5634

Abstract: A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).

Abstract translation: 一种具有在存储器核心（401）上制造的双位动态参考架构（408,410）的基于核心的多位存储器（400）。 在存储器核心（401）上制造第一参考阵列（408）和第二参考阵列（410），使得包括第一参考阵列（408）的一个单元（182）的参考单元对（185）和相应的 对第二参考阵列（410）的单元（184）进行读取和平均以提供用于读取数据阵列的参考电压。

公开(公告)号：US07221587B2

公开(公告)日：2007-05-22

申请号：US11126738

申请日：2005-05-11

Applicant: Minoru Yamashita ,  Kazuhiro Kurihara ,  Hiroaki Wada

Inventor： Minoru Yamashita ,  Kazuhiro Kurihara ,  Hiroaki Wada

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/12

Abstract: The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page, when the multiple bits are programmed in the multiple pages. The page is a selection unit and is composed of a given number of the memory cells located on a same word line. An unnecessary stress of programming is not applied to the memory cells that are not to be programmed, by increasing the distance between the memory cells to be programmed simultaneously.

Abstract translation: 本发明的半导体器件包括列解码器（选择和写入电路），其选择彼此不相邻的多个页面，以便当多位数据同时编程所选页面的存储器单元中的多个位时 在多页中编程。 该页面是选择单元，并且由位于相同字线上的给定数量的存储器单元组成。 通过增加要同时编程的存储单元之间的距离，不会对不需要编程的存储单元施加不必要的编程压力。

公开(公告)号：US20070047369A1

公开(公告)日：2007-03-01

申请号：US11514391

申请日：2006-08-30

Applicant: Hiroki Murakami ,  Kazuhiro Kurihara

Inventor： Hiroki Murakami ,  Kazuhiro Kurihara

IPC: G11C8/00

CPC classification number: G11C11/413 ,  G11C16/102 ,  G11C16/105

Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.

Abstract translation: 一种半导体器件包括：具有全部要被擦除并具有闪存单元的数据的第一扇区（12）; 具有全部要保留并具有闪存单元的数据的第二扇区（14）; 扇区选择电路（16）在擦除第一扇区中的数据期间从扇区中选择一对扇区，所述一对扇区是第一扇区和第二扇区; 以及保持第二扇区的数据的SRAM阵列（存储）（30）。 本发明可以提供一种半导体器件，其中使用了减少数量的扇区选择电路，使得可以减小存储单元阵列的面积并提供一种控制半导体器件的方法。

公开(公告)号：US07113442B2

公开(公告)日：2006-09-26

申请号：US11126701

申请日：2005-05-11

Applicant: Kazuhiro Kurihara

Inventor： Kazuhiro Kurihara

IPC: G11C7/00

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C16/12 ,  H02M3/07

Abstract: A non-volatile semiconductor memory includes a first pump starting to operate at a first timing and producing a first voltage, a second pump starting to operate at a second timing following the first timing and driving a given node at a second voltage, the given node being connected to a non-volatile semiconductor memory cell, and a booster boosting the given node using the first voltage at the second timing.

Abstract translation: 非易失性半导体存储器包括开始在第一定时操作并产生第一电压的第一泵，第二泵开始在第一定时之后的第二定时操作并以第二电压驱动给定节点，给定节点 连接到非易失性半导体存储器单元，以及升压器，在第二定时使用第一电压升压给定的节点。