公开(公告)号：US20110264990A1

公开(公告)日：2011-10-27

申请号：US12766163

申请日：2010-04-23

申请人： Jun Sawada

发明人： Jun Sawada

IPC分类号： G06F11/07

CPC分类号： G06F11/3608

摘要： A verification tool receives a finite precision definition for an approximation of an infinite precision numerical function implemented in a processor in the form of a polynomial of bounded functions. The verification tool receives a domain for verifying outputs of segments associated with the infinite precision numerical function. The verification tool splits the domain into at least two segments, wherein each segment is non-overlapping with any other segment and converts, for each segment, a polynomial of bounded functions for the segment to a simplified formula comprising a polynomial, an inequality, and a constant for a selected segment. The verification tool calculates upper bounds of the polynomial for the at least two segments, beginning with the selected segment and reports the segments that violate a bounding condition.

摘要翻译： 验证工具接收有限精度定义，用于以有界函数的多项式的形式在处理器中实现的无限精度数值函数的近似。 验证工具接收用于验证与无限精度数值函数相关联的段的输出的域。 验证工具将域分成至少两个段，其中每个段与任何其他段不重叠，并且对于每个段将用于该段的有界函数的多项式转换为包括多项式，不等式和 所选段的常数。 验证工具从所选择的段开始计算至少两个段的多项式的上限，并报告违反边界条件的段。

公开(公告)号：US20090177870A1

公开(公告)日：2009-07-09

申请号：US11968692

申请日：2008-01-03

申请人： Bruce M. Fleischer ,  Hung C. Ngo ,  Jun Sawada

发明人： Bruce M. Fleischer ,  Hung C. Ngo ,  Jun Sawada

IPC分类号： G06F9/305 ,  G06F13/00

CPC分类号： G06F9/30032 ,  G06F7/762 ,  G06F7/766 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3826

摘要： A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit.

摘要翻译： 一种在置换单元中提供布线效率的方法。 多个选择器从多个寄存器文件接收输入数据和共享控制信号。 置换单元包括耦合到多个逻辑与门的多个多路复用器（MUX）。 多个逻辑与门被耦合到多个逻辑或门。 逻辑“与”门与逻辑或门物理分离。 逻辑与门接收来自选择器的一个或多个输出数据信号的输入。 逻辑或门组合来自逻辑与门的一个或多个输出信号，并提供来自置换单元的输出数据。

公开(公告)号：US07272624B2

公开(公告)日：2007-09-18

申请号：US10675674

申请日：2003-09-30

申请人： Wendy Ann Belluomini ,  Hung Cai Ngo ,  Jun Sawada

发明人： Wendy Ann Belluomini ,  Hung Cai Ngo ,  Jun Sawada

IPC分类号： G06F7/52

CPC分类号： G06F7/5338 ,  G06F7/483 ,  G06F7/533 ,  G06F7/5443 ,  G06F2207/3872

摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

摘要翻译： 乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。 融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器， 在输出节点维护该值。 编码器选择器单元并行操作以通常同时产生部分乘积位。 编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

公开(公告)号：US20050239440A1

公开(公告)日：2005-10-27

申请号：US10829571

申请日：2004-04-22

申请人： Yen-Fu Chen ,  John Handy-Bosma ,  Jun Sawada ,  Mei Selvage ,  Keith Walker

发明人： Yen-Fu Chen ,  John Handy-Bosma ,  Jun Sawada ,  Mei Selvage ,  Keith Walker

IPC分类号： H04L29/06 ,  H04M1/66 ,  H04W12/12

CPC分类号： H04L63/0838 ,  H04L63/0853 ,  H04W12/06 ,  H04W12/12

摘要： A client device authenticated a one-time pad table stored in the client device, and a matching table maintained by a service provider. When a request for service is posted from the client to the service provider, the next unused pad is exchanged and verified with the current state of the service provider's copy of the table. If the OTP is the next unused code, service is granted, else the user is challenged to identify himself, which when successfully completed results in the client device being downloaded with a new OTP table, replacing the compromised table. Use of service by a cloned device causes the OTP table at the service provider to become out of synchronization with the authentic device's copy of the table, thereby setting up the ability to detect the fraud, stop the service consumption by the clone, and reprogram the authentic device to allow for uninterrupted service.

摘要翻译： 客户端设备认证存储在客户端设备中的一次性填充表，以及由服务提供商维护的匹配表。 当从客户端向服务提供商发布服务请求时，下一个未使用的邮箱将与服务提供商的表副本的当前状态进行交换和验证。 如果OTP是下一个未使用的代码，则授予服务，否则用户将面临挑战，即自己识别，当成功完成导致客户端设备正在使用新的OTP表进行下载时，替换受损表。 使用克隆设备的服务会导致服务提供商的OTP表与正版设备的表副本不同步，从而设置检测到欺诈的能力，停止克隆的服务消耗，并重新编程 真实的设备，允许不间断的服务。

公开(公告)号：US20120062428A1

公开(公告)日：2012-03-15

申请号：US13320894

申请日：2010-03-02

申请人： Daigo Imano ,  Jun Sawada ,  Takeshi Yamaguchi

发明人： Daigo Imano ,  Jun Sawada ,  Takeshi Yamaguchi

IPC分类号： H01Q1/24

CPC分类号： H04M1/18 ,  H01Q1/243 ,  H01Q1/44 ,  H01Q7/00 ,  H01Q9/16 ,  H01Q9/42 ,  H05K5/061

摘要： There is provided a portable radio that exhibits high waterproof property and dust resistance property without impairing toughness and antenna performance while pursuing a smaller size.A portable radio 100 has a first case member 11 and a second case member 15 to be joined to a surrounding area of an opening of the first case member 11 by way of a soft seal member 13 and houses a circuit board 19 connected to an antenna element 17 within a case. The seal member 13 has an annular structure including a first extension part 35 made of a nonconductive material and a second extension part 37 to be connected to both ends of the first extension part 35, in which a conductive material included in at least a portion of the second extension part serves as the antenna element, a passive element, and an earth line. A hardness of the seal member 13 exhibits substantially the same hardness in both the first extension part 35 and the second extension part 37.

摘要翻译： 提供了一种便携式收音机，其具有高防水性和防尘性，而不损害韧性和天线性能，同时追求更小的尺寸。 便携式收音机100具有通过软密封部件13与第一壳体部件11的开口的周围区域接合的第一壳体部件11和第二壳体部件15，并容纳连接到天线的电路基板19 案件内的元件17。 密封构件13具有环形结构，其包括由非导电材料制成的第一延伸部分35和第二延伸部分37，第二延伸部分37连接到第一延伸部分35的两端，其中包括在至少一部分 第二延伸部分用作天线元件，无源元件和地线。 密封构件13的硬度在第一延伸部35和第二延伸部37两者中都具有相同的硬度。

公开(公告)号：US20060156805A1

公开(公告)日：2006-07-20

申请号：US11315268

申请日：2005-12-23

申请人： Jun Sawada

发明人： Jun Sawada

IPC分类号： A63B53/00

CPC分类号： G01L15/00 ,  G01M9/06

摘要： A pressure distribution measurement system for measuring a pressure distribution on a measurement object. A flexible sheet-form pressure detection member includes a plurality of pressure passages extending in parallel and a pressure detection hole opened in each of the pressure passages is affixed to a surface of an outer plate of a main wing W of an airplane. Each of the pressure passages is connected to a pressure measurement device via a pressure pipeline. Because the pressure detection hole is opened in the pressure detection member, that is, the pressure detection hole is not required to be opened in the outer plate of the main wing, the outer plate is not damaged. Further, because the flexible sheet-form pressure detection member conforms well to the three dimensionally curved surface of the outer plate and has a small thickness, the airflow is hardly disturbed at all, thereby enhancing pressure distribution measurement accuracy.

摘要翻译： 一种用于测量测量对象上的压力分布的压力分布测量系统。 柔性片状压力检测构件包括平行延伸的多个压力通道，并且在每个压力通道中打开的压力检测孔被固定到飞机的主翼W的外板的表面上。 每个压力通道通过压力管线连接到压力测量装置。 由于在压力检测部件中压力检测孔被打开，也就是说，不需要在主翼的外板中打开压力检测孔，所以外板不会被损坏。 此外，由于柔性片状压力检测部件与外板的三维曲面良好一致，所以厚度小，所以气流几乎不受到干扰，从而提高了压力分布测量精度。

公开(公告)号：US20060020863A1

公开(公告)日：2006-01-26

申请号：US10896505

申请日：2004-07-22

申请人： Andrew Martin ,  Chandler McDowell ,  Robert Montoye ,  Jun Sawada

发明人： Andrew Martin ,  Chandler McDowell ,  Robert Montoye ,  Jun Sawada

IPC分类号： G01R31/28

CPC分类号： G11C29/32 ,  G01R31/318572 ,  G11C11/41 ,  G11C2029/3202

摘要： A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.

摘要翻译： 一种用于从锁存器的矩阵阵列中的特定锁存器扫描数据的方法和系统。 矩阵阵列由垂直选择线和水平数据线组成。 每个锁存器通过晶体管耦合在选择器线和数据线的交叉点处。 通过接通晶体管，可以选择性地读取或写入锁存器的内容。

公开(公告)号：US09274751B2

公开(公告)日：2016-03-01

申请号：US11776454

申请日：2007-07-11

申请人： Wendy Ann Belluomini ,  Hung Cai Ngo ,  Jun Sawada

发明人： Wendy Ann Belluomini ,  Hung Cai Ngo ,  Jun Sawada

IPC分类号： G06F7/533 ,  G06F7/483 ,  G06F7/544

CPC分类号： G06F7/5338 ,  G06F7/483 ,  G06F7/533 ,  G06F7/5443 ,  G06F2207/3872

摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

摘要翻译： 乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。 融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器， 在输出节点维护该值。 编码器选择器单元并行操作以通常同时产生部分乘积位。 编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

公开(公告)号：US08397187B2

公开(公告)日：2013-03-12

申请号：US12766163

申请日：2010-04-23

申请人： Jun Sawada

发明人： Jun Sawada

IPC分类号： G06F17/50 ,  G06F17/15 ,  G06F17/17 ,  G01R35/00 ,  G01D3/00

CPC分类号： G06F11/3608

摘要： A verification tool receives a finite precision definition for an approximation of an infinite precision numerical function implemented in a processor in the form of a polynomial of bounded functions. The verification tool receives a domain for verifying outputs of segments associated with the infinite precision numerical function. The verification tool splits the domain into at least two segments, wherein each segment is non-overlapping with any other segment and converts, for each segment, a polynomial of bounded functions for the segment to a simplified formula comprising a polynomial, an inequality, and a constant for a selected segment. The verification tool calculates upper bounds of the polynomial for the at least two segments, beginning with the selected segment and reports the segments that violate a bounding condition.

摘要翻译： 验证工具接收有限精度定义，用于以有界函数的多项式的形式在处理器中实现的无限精度数值函数的近似。 验证工具接收用于验证与无限精度数值函数相关联的段的输出的域。 验证工具将域分成至少两个段，其中每个段与任何其他段不重叠，并且对于每个段将用于该段的有界函数的多项式转换为包括多项式，不等式和 所选段的常数。 验证工具从所选择的段开始计算至少两个段的多项式的上限，并报告违反边界条件的段。

公开(公告)号：US20120278773A1

公开(公告)日：2012-11-01

申请号：US13097171

申请日：2011-04-29

申请人： Viresh Paruthi ,  Peter Anthony Sandon ,  Jun Sawada

发明人： Viresh Paruthi ,  Peter Anthony Sandon ,  Jun Sawada

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/504 ,  G06F9/4498 ,  G06F17/5022

摘要： A method, system, and computer program product for verification of a state transition machine (STM) are provided in the illustrative embodiments. The STM representing the operation of a circuit configured to perform a computation is received. A segment of the STM is selected from a set of segments of the STM. A set of properties of the segment is determined. The set of properties is translated into a hardware description to form a translation. The segment is verified by verifying whether all relationships between a pre-condition and a post condition in the translation hold true for any set of inputs and any initial state of a hardware design under test. A verification result for the segment is generated. Verification results for each segment in the set of segments are combined to generate a verification result for the STM.

摘要翻译： 在说明性实施例中提供了用于验证状态转换机（STM）的方法，系统和计算机程序产品。 接收表示被配置为执行计算的电路的操作的STM。 从STM的一组段中选择STM的一段。 确定该段的一组属性。 该属性集被翻译成硬件描述以形成一个翻译。 通过验证翻译中的前提条件和后期条件之间的所有关系是否适用于任何一组输入以及所测试的硬件设计的任何初始状态来验证该段。 生成段的验证结果。 组合段中每个段的验证结果，以生成STM的验证结果。