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1.发明申请TSV FOR 3D PACKAGING OF SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权用于半导体器件的3D封装的TSV及其制造方法公开(公告)号：US20120153496A1
公开(公告)日：2012-06-21
申请号：US13031861
申请日：2011-02-22
申请人： Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
发明人： Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
CPC分类号： H01L21/76898 , H01L24/03 , H01L24/05 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05669 , H01L2224/13009 , H01L2224/24011 , H01L2224/24146 , H01L2224/24226 , H01L2224/245 , H01L2224/27416 , H01L2224/27452 , H01L2224/2761 , H01L2224/27616 , H01L2224/29187 , H01L2224/821 , H01L2224/82101 , H01L2224/82143 , H01L2224/83001 , H01L2224/83013 , H01L2224/83143 , H01L2224/83192 , H01L2224/92 , H01L2224/9202 , H01L2224/92244 , H01L2225/06513 , H01L2225/06541 , H01L2924/01029 , H01L2924/00014 , H01L2224/03 , H01L2224/27 , H01L2224/83 , H01L2924/01074 , H01L2924/01013
摘要： The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.
摘要翻译： 本发明涉及一种用于3D封装的硅通孔（TSV），用于集成半导体器件及其制造方法，更具体地，涉及一种用于半导体器件的3D封装的贯穿硅通孔（TSV），其具有能够 提高生产效率，具有非常高的导电性和最小化电信号延迟，而不用通过在低温状态下自对准衬底并顺序地接合多个半导体管芯（或半导体芯片）而使用载体晶片，以及 制造相同。
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公开(公告)号：US20130256911A1
公开(公告)日：2013-10-03
申请号：US13391063
申请日：2010-02-22
申请人： Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
发明人： Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
IPC分类号： H01L23/488 , H01L21/50
CPC分类号： H01L23/488 , H01L21/50 , H01L24/26 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/26145 , H01L2224/27013 , H01L2224/29139 , H01L2224/2919 , H01L2224/29191 , H01L2224/32145 , H01L2224/48091 , H01L2224/73215 , H01L2224/73265 , H01L2224/82143 , H01L2224/83002 , H01L2224/83051 , H01L2224/83143 , H01L2224/83192 , H01L2224/9205 , H01L2224/92147 , H01L2225/0651 , H01L2225/06562 , H01L2225/06593 , H01L2924/00014 , H01L2924/10253 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor chip stack package and a manufacturing method thereof, and more particularly, to a semiconductor chip stack package and a manufacturing method thereof in which a plurality of chips can be rapidly arranged and bonded without a precise device or operation so as to improve productivity
摘要翻译： 半导体芯片堆叠封装及其制造方法技术领域本发明涉及一种半导体芯片堆叠封装及其制造方法，更具体地，涉及一种半导体芯片堆叠封装及其制造方法，其中可以在没有精确的装置或操作的情况下快速地布置和粘合多个芯片 以提高生产率
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公开(公告)号：US08722513B2
公开(公告)日：2014-05-13
申请号：US13391063
申请日：2011-02-22
申请人： Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
发明人： Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
CPC分类号： H01L23/488 , H01L21/50 , H01L24/26 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/26145 , H01L2224/27013 , H01L2224/29139 , H01L2224/2919 , H01L2224/29191 , H01L2224/32145 , H01L2224/48091 , H01L2224/73215 , H01L2224/73265 , H01L2224/82143 , H01L2224/83002 , H01L2224/83051 , H01L2224/83143 , H01L2224/83192 , H01L2224/9205 , H01L2224/92147 , H01L2225/0651 , H01L2225/06562 , H01L2225/06593 , H01L2924/00014 , H01L2924/10253 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor chip stack package and a manufacturing method thereof, and more particularly, to a semiconductor chip stack package and a manufacturing method thereof in which a plurality of chips can be rapidly arranged and bonded without a precise device or operation so as to improve productivity.
摘要翻译： 半导体芯片堆叠封装及其制造方法技术领域本发明涉及一种半导体芯片堆叠封装及其制造方法，更具体地，涉及一种半导体芯片堆叠封装及其制造方法，其中可以在没有精确的装置或操作的情况下快速地布置和粘合多个芯片 以提高生产率。
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公开(公告)号：US08513061B2
公开(公告)日：2013-08-20
申请号：US13031861
申请日：2011-02-22
申请人： Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
发明人： Jae-Hak Lee , Chang-Woo Lee , Joon-Yub Song , Tae-Ho Ha
CPC分类号： H01L21/76898 , H01L24/03 , H01L24/05 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05669 , H01L2224/13009 , H01L2224/24011 , H01L2224/24146 , H01L2224/24226 , H01L2224/245 , H01L2224/27416 , H01L2224/27452 , H01L2224/2761 , H01L2224/27616 , H01L2224/29187 , H01L2224/821 , H01L2224/82101 , H01L2224/82143 , H01L2224/83001 , H01L2224/83013 , H01L2224/83143 , H01L2224/83192 , H01L2224/92 , H01L2224/9202 , H01L2224/92244 , H01L2225/06513 , H01L2225/06541 , H01L2924/01029 , H01L2924/00014 , H01L2224/03 , H01L2224/27 , H01L2224/83 , H01L2924/01074 , H01L2924/01013
摘要： The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.
摘要翻译： 本发明涉及一种用于3D封装的硅通孔（TSV），用于集成半导体器件及其制造方法，更具体地，涉及一种用于半导体器件的3D封装的贯穿硅通孔（TSV），其具有能够 提高生产效率，具有非常高的导电性和最小化电信号延迟，而不用通过在低温状态下自对准衬底并顺序地接合多个半导体管芯（或半导体芯片）而使用载体晶片，以及 制造相同。
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