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    Method and apparatus for selectively utilizing information within a semiconductor device
    1.
    发明授权
    Method and apparatus for selectively utilizing information within a semiconductor device 有权
    用于选择性地利用半导体器件内的信息的方法和装置

    公开(公告)号：US07917825B2

    公开(公告)日：2011-03-29

    申请号：US11639161

    申请日：2006-12-15

    Applicant: Joo-Sang Lee

    Inventor： Joo-Sang Lee

    IPC: G01R31/28

    CPC classification number: G11C29/18 ,  G11C2029/3602

    Abstract: Embodiments of the present invention include an apparatus to selectively provide information within a device to enable the device to perform a function. The apparatus comprises a generator unit to generate information for the device to perform the function, a receiver unit to receive information from a source and provide the received information for the device, and a storage unit. The storage unit selectively stores the information from the generator unit and the receiver unit for use by the device in accordance with an information selection signal and a mode signal indicating entry of the device into a particular device mode. Information from the receiver unit is stored in the storage unit in response to availability of information from the receiver unit and the mode signal indicating entry of the device into the particular device mode.

    Abstract translation: 本发明的实施例包括一种用于选择性地在设备内提供信息以使设备能够执行功能的设备。 该装置包括：生成装置，用于产生用于装置执行功能的信息;接收器单元，用于从源接收信息并提供所接收的装置信息;以及存储单元。 存储单元根据信息选择信号和指示设备进入特定设备模式的模式信号来选择性地存储来自发生器单元和接收器单元的信息以供设备使用。 响应于来自接收器单元的信息的可用性和指示设备进入特定设备模式的模式信号，来自接收器单元的信息被存储在存储单元中。

    Method and apparatus for selectively utilizing information within a semiconductor device
    2.
    发明申请
    Method and apparatus for selectively utilizing information within a semiconductor device 有权
    用于选择性地利用半导体器件内的信息的方法和装置

    公开(公告)号：US20080148007A1

    公开(公告)日：2008-06-19

    申请号：US11639161

    申请日：2006-12-15

    Applicant: Joo-Sang Lee

    Inventor： Joo-Sang Lee

    IPC: G06F12/00 ,  G06F9/34

    CPC classification number: G11C29/18 ,  G11C2029/3602

    Abstract: Embodiments of the present invention include an apparatus to selectively provide information within a device to enable the device to perform a function. The apparatus comprises a generator unit to generate information for the device to perform the function, a receiver unit to receive information from a source and provide the received information for the device, and a storage unit. The storage unit selectively stores the information from the generator unit and the receiver unit for use by the device in accordance with an information selection signal and a mode signal indicating entry of the device into a particular device mode. Information from the receiver unit is stored in the storage unit in response to availability of information from the receiver unit and the mode signal indicating entry of the device into the particular device mode.

    Abstract translation: 本发明的实施例包括一种用于选择性地在设备内提供信息以使设备能够执行功能的设备。 该装置包括：生成装置，用于产生用于装置执行功能的信息;接收器单元，用于从源接收信息并提供所接收的装置信息;以及存储单元。 存储单元根据信息选择信号和指示设备进入特定设备模式的模式信号来选择性地存储来自发生器单元和接收器单元的信息以供设备使用。 响应于来自接收器单元的信息的可用性和指示设备进入特定设备模式的模式信号，来自接收器单元的信息被存储在存储单元中。

    Apparatus for varying data input/output path in semiconductor memory device
    4.
    发明授权
    Apparatus for varying data input/output path in semiconductor memory device 失效

    公开(公告)号：US06529419B2

    公开(公告)日：2003-03-04

    申请号：US10028431

    申请日：2001-12-28

    Applicant: Joo Sang Lee

    Inventor： Joo Sang Lee

    IPC: G11C1604

    CPC classification number: G11C7/1051 ,  G11C7/1045 ,  G11C7/1048

    Abstract: An apparatus for varying a data input/output path in a memory device, includes DBSAs amplifying a signal loaded on a data bus, fuse circuits producing output signals of specific levels respectively in accordance with whether or not fuses are cut, input multiplexers each of which selects either an external signal inputted through a corresponding pad or another external signal inputted through a pad next to the corresponding pad in accordance with the output signals of the fuse circuits, and applies the selected signal to a write driver, and data input/output parts including output multiplexers, each of the output multiplexers selecting a signal outputted from either a corresponding one of the DBSAs or one next to the corresponding DBSA in accordance with the output signals of the fuse circuits, and outputting the selected signal through a corresponding pad.

    Fuse repair circuit for semiconductor memory circuit
    5.
    发明授权
    Fuse repair circuit for semiconductor memory circuit 有权
    半导体存储电路保险丝修复电路

    公开(公告)号：US6111798A

    公开(公告)日：2000-08-29

    申请号：US247523

    申请日：1999-02-10

    Applicant: Joo Sang Lee

    Inventor： Joo Sang Lee

    IPC: G11C29/00 ,  G11C7/00

    CPC classification number: G11C29/785 ,  G11C29/80

    Abstract: A fuse repair circuit for a semiconductor memory device includes a cell array provided with a row redundancy and a column redundancy and a fuse block for driving the row redundancy during a RAS cycle and driving the column redundancy during a CAS cycle, wherein the fuse block consists of an address input unit for selectively outputting a row address or a column address in accordance with switching signals, a plurality of fuse units, wherein redundancy information of a defective cell is programmed, for comparing an inputted address with the programmed redundancy information, and a redundancy driving unit for outputting a matching signal for driving the row redundancy or the column redundancy when the inputted address and the programmed redundancy information are identical.

    Abstract translation: 一种用于半导体存储器件的保险丝修复电路包括具有行冗余和列冗余的单元阵列和用于在RAS周期期间驱动行冗余的熔丝块，并且在CAS周期期间驱动列冗余，其中熔丝块组成 一个地址输入单元，用于根据切换信号选择性地输出行地址或列地址;多个保险丝单元，其中对缺陷单元的冗余信息进行编程，用于将输入的地址与编程的冗余信息进行比较;以及 冗余驱动单元，用于当输入的地址和编程的冗余信息相同时，输出用于驱动行冗余或列冗余的匹配信号。

    Memory system with reduced refresh current
    9.
    发明授权
    Memory system with reduced refresh current 失效
    内存系统刷新电流降低

    公开(公告)号：US06862238B1

    公开(公告)日：2005-03-01

    申请号：US10672244

    申请日：2003-09-25

    Applicant: Joo-Sang Lee

    Inventor： Joo-Sang Lee

    IPC: G11C11/406 ,  G11C7/00

    CPC classification number: G11C11/40622 ,  G11C11/406

    Abstract: The present invention is a random access memory device with reduced refresh current and method for use in the same. The memory device includes a memory array with a plurality of memory cells. The memory cells are configured to hold a charge. A command block is coupled to the memory bank and is configured to receive refresh commands that are used to periodically refresh the memory cells. A detection circuit is coupled to the command block and to the memory array. The detection circuit is configured to store a hit detect signal when the memory array is accessed. The detection circuit also receives the refresh command. The detections circuit enables block select signals only when the hit detect signal is stored while the refresh command is received.

    Abstract translation: 本发明是具有降低的刷新电流的随机存取存储器件及其使用方法。 存储器件包括具有多个存储器单元的存储器阵列。 存储器单元被配置为保持电荷。 命令块被耦合到存储体并且被配置为接收用于周期性地刷新存储器单元的刷新命令。 检测电路耦合到命令块和存储器阵列。 检测电路被配置为在访问存储器阵列时存储命中检测信号。 检测电路也接收刷新命令。 只有当接收到刷新命令时存储命中检测信号时，检测电路才能使能块选择信号。

    Apparatus for selecting bank in semiconductor memory device
    10.
    发明授权
    Apparatus for selecting bank in semiconductor memory device 失效

    公开(公告)号：US06570808B2

    公开(公告)日：2003-05-27

    申请号：US10028672

    申请日：2001-12-28

    Applicant: Joo Sang Lee

    Inventor： Joo Sang Lee

    IPC: G11C700

    CPC classification number: G11C29/88 ,  G11C8/12 ,  G11C29/883

    Abstract: An apparatus for selecting banks in a semiconductor memory device provides a half-chip by adjusting all bits including the most significant bit (MSB) of bank addresses to select normal banks even if degraded banks are included in both upper and lower bank blocks. In a memory including an upper bank block and a lower bank block which are constructed with a plurality of banks selectable by a plurality of bank addresses, an apparatus for selecting the banks includes a plurality of bank address control parts each corresponding to one address bit of the bank addresses, each of the bank address control part applying a fixed logic value to the upper and lower bank blocks according to a selective cutting of at least one of the fuses, and each of the bank address control parts applying either a corresponding bank address bit input thereto or a bank address bit just below the corresponding bank address bit to the upper and lower bank blocks.

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